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AD8055AR Datasheet(PDF) 10 Page - Analog Devices |
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AD8055AR Datasheet(HTML) 10 Page - Analog Devices |
10 / 11 page AD8055/AD8056 –10– REV. B Power Dissipation Limits With a 10 V supply (total VCC – VEE), the quiescent power dissi- pation of the AD8055 in the SOT-23-5 package is 65 mW, while the quiescent power dissipation of the AD8056 in the microSOIC is 120 mW. This translates into a 15.6 °C rise above the ambient for the SOT-23-5 package and a 24 °C rise for the microSOIC package. The power dissipated under heavy load conditions is approxi- mately equal to the supply voltage minus the output voltage, times the load current, plus the quiescent power computed above. This total power dissipation is then multiplied by the thermal resistance of the package to find the temperature rise, above ambient, of the part. The junction temperature should be kept below 150 °C. The AD8055 in the SOT-23-5 package can dissipate 270 mW while the AD8056 in the microSOIC package can dissipate 325 mW (at 85 °C ambient) without exceeding the maximum die temperature. In the case of the AD8056, this is greater than 1.5 V rms into 50 Ω, enough to accommodate a 4 V p-p sine-wave signal on both outputs simultaneously. But since each output of the AD8055 or AD8056 is capable of supplying as much as 110 mA into a short circuit, a continuous short circuit condition will exceed the maximum safe junction temperature. Resistor Selection The following table is provided as a guide to resistor selection for maintaining gain flatness vs. frequency for various values of gain. –3 dB Bandwidth Gain RF ( )RI ( ) (MHz) +1 0 — 300 +2 402 402 160 +5 1k 249 45 +10 909 100 20 Driving Capacitive Loads When driving a capacitive load, most op amps will exhibit peak- ing in the frequency response just before the frequency rolls off. Figure 36 shows the responses for an AD8056 running at a gain of +2, with a 100 Ω load that is shunted by various values of capacitance. It can be seen that under these conditions, the part is still stable with capacitive loads of up to 30 pF. FREQUENCY – MHz 5 4 –5 0.3 500 1 10 100 1 –2 –3 –4 3 2 –1 0 CL = 30pF CL = 20pF CL = 10pF CL = 0pF 402 CL 100 402 50 VIN = 0dBm Figure 36. Capacitive Load Drive In general, to minimize peaking or to ensure the stability for larger values of capacitive loads, a small series resistor, RS, can be added between the op amp output and the capacitor, CL. For the setup depicted in Figure 37, the relationship between RS and CL was empirically derived and is shown in Figure 38. RS was chosen to produce less than 1 dB of peaking in the frequency response. Note also that after a sharp rise RS quickly settles to about 25 Ω. VIN = 0dBm 50 AD8055 VOUT +5V –5V 402 402 6 7 2 3 4 CL 0.1 F 10 F 0.1 F 10 F RS FET PROBE Figure 37. Setup for RS vs. CL CL – pF 0 270 10 20 30 40 50 60 40 0 35 20 15 10 5 30 25 Figure 38. RS vs. CL |
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