REV. A

–8–

AD807

A lower damping ratio allows a faster frequency acquisition;

generally the acquisition time scales directly with the capacitor

value. However, at damping ratios approaching one, the acquisi-

tion time no longer scales directly with capacitor value. The

acquisition time has two components: frequency acquisition and

phase acquisition. The frequency acquisition always scales with

capacitance, but the phase acquisition is set by the loop band-

width of the PLL and is independent of the damping ratio.

Thus, the 0.06% fractional loop bandwidth sets a minimum

acquisition time of 2000 bit periods. Note the acquisition time

for a damping factor of one is 15,000 bit periods. This com-

prises 13,000 bit periods for frequency acquisition and 2,000 bit

periods for phase acquisition. Compare this to the 400,000 bit

periods acquisition time specified for a damping ratio of 5; this

consists entirely of frequency acquisition, and the 2,000 bit

periods of phase acquisition is negligible.

While a lower damping ratio affords faster acquisition, it also al-

lows more peaking in the jitter transfer response (jitter peaking).

For example, with a damping ratio of 10, the jitter peaking is

0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.

Center Frequency Clamp (Figure 19)

An N-channel FET circuit can be used to bring the AD807

VCO center frequency to within

±10% of 155 MHz when

SDOUT indicates a Loss of Signal (LOS). This effectively re-

duces the frequency acquisition time by reducing the frequency

error between the VCO frequency and the input data frequency

at clamp release. The N-FET can have “on” resistance as high

as 1 k

Ω and still attain effective clamping. However, the chosen

N-FET should have greater than 10 M

Ω “off” resistance and

less than 100 nA leakage current (source and drain) so as not to

alter normal PLL performance.

1

2

5

6

7

3

4

8

16

15

12

11

10

14

13

9

SDOUT

PIN

NIN

THRADJ

DATAOUTN

DATAOUTP

CLKOUTN

CLKOUTP

CF1

CF2

AD807

N_FET

Figure 19. Center Frequency Clamp Schematic

10

20k

10k

100

1k

C

D

PEAK

0.1

0.12

0.15

0.08

0.22

0.06

0.33

0.04

FREQUENCY IN kHz

POSITIVE

PEAK

DETECTOR

NEGATIVE

PEAK

DETECTOR

LEVEL

SHIFT

DOWN

LEVEL

SHIFT

UP

∑

THRESHOLD

BIAS

PIN

NIN

SDOUT

IHYS

+

+

AD807

COMPARATOR STAGES

& CLOCK RECOVERY PLL

ITHR

Figure 17. Signal Level Detect Circuit Block Diagram

Phase-Locked Loop

The phase-locked loop recovers clock and retimes data from

NRZ data. The architecture uses a frequency detector to aid ini-

tial frequency acquisition; refer to Figure 18 for a block dia-

gram. Note the frequency detector is always in the circuit. When

the PLL is locked, the frequency error is zero and the frequency

detector has no further effect. Since the frequency detector is al-

ways in the circuit, no control functions are needed to initiate

acquisition or change mode after acquisition.

VCO

RETIMING

DEVICE

Φ

DET

∑

DATA

INPUT

1

S

S + 1

RECOVERED CLOCK

OUTPUT

RETIMED DATA

OUTPUT

Figure 18. PLL Block Diagram

The frequency detector delivers pulses of current to the charge

pump to either raise or lower the frequency of the VCO. During

the frequency acquisition process the frequency detector output

is a series of pulses of width equal to the period of the VCO.

These pulses occur on the cycle slips between the data fre-

quency and the VCO frequency. With a maximum density data

pattern (1010 . . . ), every cycle slip will produce a pulse at the

frequency detector output. However, with random data, not

every cycle slip produces a pulse. The density of pulses at the

frequency detector output increases with the density of data

transitions. The probability that a cycle slip will produce a pulse

increases as the frequency error approaches zero. After the fre-

quency error has been reduced to zero, the frequency detector

output will have no further pulses. At this point the PLL begins

the process of phase acquisition, with a settling time of roughly

2000 bit periods.

Jitter caused by variations of density of data transitions (pattern

jitter) is virtually eliminated by use of a new phase detector (pat-

ented). Briefly, the measurement of zero phase error does not

cause the VCO phase to increase to above the average run rate

set by the data frequency. The jitter created by a 2

random code is 1/2 degree, and this is small compared to ran-

dom jitter.

The jitter bandwidth for the PLL is 0.06% of the center fre-

quency. This figure is chosen so that sinusoidal input jitter at

92 kHz will be attenuated by 3 dB.

The damping ratio of the PLL is user programmable with a

single external capacitor. At 155 MHz, a damping ratio of 5 is

obtained with a 0.15

µF capacitor. More generally, the damping

× C