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AD8300AN Datasheet(PDF) 2 Page - Analog Devices |
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AD8300AN Datasheet(HTML) 2 Page - Analog Devices |
2 / 8 page REV. A –2– AD8300–SPECIFICATIONS +3 V OPERATION Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N [Note 1] 12 Bits Relative Accuracy INL –2 ±1/2 +2 LSB Differential Nonlinearity 2 DNL Monotonic –1 ±1/2 +1 LSB Zero-Scale Error VZSE Data = 000H +1/2 +3 mV Full-Scale Voltage3 VFS Data = FFFH 2.039 2.0475 2.056 Volts Full-Scale Tempco TCVFS [Notes 3, 4] 16 ppm/ °C ANALOG OUTPUT Output Current (Source) IOUT Data = 800H, ∆V OUT = 5 LSB 5 mA Output Current (Sink) IOUT Data = 800H, ∆V OUT = 5 LSB 2 mA Load Regulation LREG RL = 200 Ω to ∞, Data = 800H 1.5 5 LSB Output Resistance to GND ROUT Data = 000H 30 Ω Capacitive Load CL No Oscillation 4 500 pF LOGIC INPUTS Logic Input Low Voltage VIL 0.6 V Logic Input High Voltage VIH 2.1 V Input Leakage Current IIL 10 µA Input Capacitance CIL 10 pF INTERFACE TIMING SPECIFICATIONS 4, 5 Clock Width High tCH 40 ns Clock Width Low tCL 40 ns Load Pulsewidth tLDW 50 ns Data Setup tDS 15 ns Data Hold tDH 15 ns Clear Pulsewidth tCLRW 40 ns Load Setup tLD1 15 ns Load Hold tLD2 40 ns Select tCSS 40 ns Deselect tCSH 40 ns AC CHARACTERISTICS4 Voltage Output Settling Time tS To ±0.2% of Full Scale 7 µs To ±1 LSB of Final Value6 14 µs Output Slew Rate SR Data = 000H to FFFH to 000H 2.0 V/ µs DAC Glitch 15 nV/s Digital Feedthrough 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL < ±1 LSB 2.7 5.5 V Positive Supply Current IDD VDD = 3 V, VIL = 0 V, Data = 000H 1.2 1.7 mA VDD = 3.6 V, VIH = 2.3 V, Data = FFFH 1.9 3.0 mA Power Dissipation PDISS VDD = 3 V, VIL = 0 V, Data = 000H 3.6 5.1 mW Power Supply Sensitivity PSS ∆V DD = ± 5% 0.001 0.005 %/% NOTES 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. 2The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3Includes internal voltage reference error. 4These parameters are guaranteed by design and not subject to production testing. 5All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. 6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. (@ VDD = +5 V 10%, –40 C ≤ T A ≤ +85 C, unless otherwise noted) |
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