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AD9822JRS Datasheet(PDF) 9 Page - Analog Devices |
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AD9822JRS Datasheet(HTML) 9 Page - Analog Devices |
9 / 15 page REV. A AD9822 –9– FUNCTIONAL DESCRIPTION The AD9822 can be operated in four different modes: 3-Channel CDS Mode, 3-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel SHA Mode. Each mode is selected by program- ming the Configuration Register through the serial interface. For more detail on CDS or SHA mode operation, see the Circuit Operation section. 3-Channel CDS Mode In 3-Channel CDS Mode, the AD9822 simultaneously samples the red, green and blue input voltages from the CCD outputs. The sampling points for each Correlated Double Sampler (CDS) are controlled by CDSCLK1 and CDSCLK2 (see Figures 8 and 9). CDSCLK1’s falling edge samples the reference level of the CCD waveform. CDSCLK2’s falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD’s reference and data levels. Next, the output voltage of each CDS amplifier is level-shifted by an Offset DAC. The voltages are then scaled by the three Program- mable Gain Amplifiers before being multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the red, green and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register. Timing for this mode is shown in Figure 1. It is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK, although this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three clock cycles. 3-Channel SHA Mode In 3-Channel SHA Mode, the AD9822 simultaneously samples the red, green and blue input voltages. The sampling point is controlled by CDSCLK2. CDSCLK2’s falling edge samples the input waveforms on each channel. The output voltages from the three SHAs are modified by the offset DACs and then scaled by the three PGAs. The outputs of the PGAs are then multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 10). With the OFFSET pin grounded, a zero volt input corresponds to the ADC’s zero-scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the AD9822. The input clamp is dis- abled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 2. CDSCLK1 should be grounded in this mode. Although not required, it is recom- mended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles. The offset and gain values for the red, green, and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register. 1-Channel CDS Mode This mode operates in the same way as the 3-Channel CDS mode. The difference is that the multiplexer remains fixed in this mode, so only the channel specified in the MUX register is processed. Timing for this mode is shown in Figure 3. 1-Channel SHA Mode This mode operates in the same way as the 3-Channel SHA mode, except that the multiplexer remains stationary. Only the channel specified in the MUX register is processed. The input signal is sampled with respect to the voltage applied to the OFFSET pin. With the OFFSET pin grounded, a zero volt input corresponds to the ADC’s zero scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the AD9822. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 4. CDSCLK1 should be grounded in this mode of operation. |
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