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AD9833BRM Datasheet(PDF) 9 Page - Analog Devices

No. de pieza AD9833BRM
Descripción Electrónicos  2.5 V to 5.5 V, 25 MHz Low Power CMOS Complete DDS
Download  18 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9833BRM Datasheet(HTML) 9 Page - Analog Devices

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AD9833
– 9–
REV PrG
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION
Serial Interface
The AD9833 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing dia-
gram for this operation is given in Figure 3.
The FSYNC input is a level triggered input that acts as a
frame synchronisation and chip enable. Data can only be
transferred into the device when FSYNC is low. To start
the serial data transfer, FSYNC should be taken low, ob-
serving the minimum FSYNC to SCLK falling edge setup
time, t7. After FSYNC goes low, serial data will be shifted
into the device's input shift register on the falling edges of
SCLK for 16 clock pulses. FSYNC may be taken high
after the sixteenth falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time,
t8. Alternatively, FSYNC can be kept low for a multiple of
16 SCLK pulses, and then brought high at the end of the
data transfer. In this way, a continuous stream of 16 bit
words can be loaded while FSYNC is held low, FSYNC
only going high after the 16th SCLK falling edge of the
last word loaded.
The SCLK can be continuous or, alternatively, the SCLK
can idle high or low between write operations.
Powering up the AD9833
The flow chart in Figure 6 shows the operating routine for
the AD9833. When the AD9833 is powered up, the part
should be reset. This will reset appropriate internal regis-
ters to zero to provide an analog output of midscale. To
avoid spurious DAC outputs while the AD9833 is being
initialized, the RESET bit should be set to 1 until the part
is ready to begin generating an output. RESET does not
reset the phase, frequency or control registers. These reg-
isters will contain invalid data and, therefore, should be set
to a known value by the user. The RESET bit should then
be set to 0 to begin generating an output. A signal will
appear at the DAC output 7 MCLK cycles after RESET is
set to 0.
Latency
Associated with each asynchronous write operation in the
AD9833 is a latency. If a selected frequency/phase register
is loaded with a new word there is a delay of 7 to 8 MCLK
cycles before the analog output will change. (There is an
uncertainty of one MCLK cycle as it depends on the posi-
tion of the MCLK rising edge when the data is loaded into
the destination register.)
The Control Register
The AD9833 contains a 16-bit control register which sets
up the AD9833 as the user wishes to operate it. All control
bits, except MODE, are sampled on the internal negative
edge of MCLK.
Table 2, on the following page, describes the individual
bits of the control register. The different functions and the
various output options from the AD9833 are described in
more detail in the section following Table 2.
To inform the AD9833 that you wish to alter the contents
of the Control register, D15 and D14 must be set to '0' as
shown below.
Table 1. Control Register
D15
D14
D13
D0
0
0
CONTROL BITS
Figure 5. Function of Control Bits
SIN
RO M
(L ow P ow er)
10-Bit DA C
VO U T
A D 9833
P hase
Accu m u lator
(28 B it)
MU X
DIV B Y
2
MU X
DIG IT AL
OU TP U T
(enab le)
SL EE P12
SLEE P 1
R E SET
OP B IT EN
DIV 2
0
1
1
0
DB15 DB14
DB13
DB12 DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
B2 8
HLB
FSELECT PSELECT
0
RESET
SLEEP1 SLEEP12
O PBITEN
0
DIV2
0
M ODE
0
MO D E + O PBITE N


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