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ADM690AN Datasheet(PDF) 11 Page - Analog Devices |
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ADM690AN Datasheet(HTML) 11 Page - Analog Devices |
11 / 16 page ADM690–ADM695 REV. A –11– ADM69x CE IN PFO PFI V CC FROM µP I/O PIN APPLIES TEST LOAD TO BATTERY LOW BATTERY SIGNAL TO µP I/O PIN +5V INPUT POWER V BATT CE OUT BATTERY 20k Ω OPTIONAL TEST LOAD 10M Ω 10M Ω Figure 20. Monitoring the Battery Status Alternate Watchdog Input Drive Circuits The watchdog feature can be enabled and disabled under pro- gram control by driving WDI with a 3-state buffer (Figure 21a). When three-stated, the WDI input will float thereby disabling the watchdog timer. WDI ADM69x WATCHDOG STROBE CONTROL INPUT Figure 21a. Programming the Watchdog Input This circuit is not entirely foolproof, and it is possible that a software fault could erroneously 3-state the buffer. This would then prevent the ADM69x from detecting that the microproces- sor is no longer operating correctly. In most cases a better method is to extend the watchdog period rather than disabling the watchdog. This may be done under program control using the circuit shown in Figure 21b. When the control input is high, the OSC SEL pin is low and the watchdog timeout is set by the external capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of 100 seconds. When the control input is low, the OSC SEL pin is driven high, selecting the internal oscillator. The 100 ms or the 1.6 s period is chosen, depending on which diode in Figure 21b is used. With D1 inserted the internal timeout is set at 100 ms, while with D2 inserted the timeout is set at 1.6 s. OSC IN OSC SEL ADM69x CONTROL INPUT* D1 D2 *LOW = INTERNAL TIMEOUT HIGH = EXTERNAL TIMEOUT Figure 21b. Programming the Watchdog Input Replacing the Backup Battery When changing the backup battery with system power on, spuri- ous resets can occur when the battery is removed. This occurs because the leakage current flowing out of the VBATT pin will charge up the stray capacitance. If the voltage on VBATT reaches within 50 mV of VCC, a reset pulse is generated. If spurious resets during battery replacement are acceptable, then no action is required. If not, then one of the following solutions should be considered: 1. A capacitor from VBATT to GND. This gives time while the capacitor is charging up to replace the battery. The leakage current will charge up the external capacitor towards the VCC level. The time taken is related to the charging current, the size of external capacitor and the voltage differential between the capacitor and the charging voltage supply. t = CEXT × VDIFF/I The maximum leakage (charging) current is 1 µA over tem- perature and VDIFF = VCC–VBATT. Therefore, the capacitor size should be chosen such that sufficient time is available to make the battery replacement. CEXT = TREQD (1 µA/(VCC–VBATT)) If a replacement time of 5 seconds is allowed and assuming a VCC of 4.5 V and a VBATT of 3 V CEXT = 3.33 µF ADM69x V BATT BATTERY C EXT Figure 22a. Preventing Spurious RESETS During Battery Replacement 2. A resistor from VBATT to GND. This will prevent the voltage on VBATT from rising to within 50 mV of VCC during battery replacement. |
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