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ADM8694AN Datasheet(PDF) 8 Page - Analog Devices |
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ADM8694AN Datasheet(HTML) 8 Page - Analog Devices |
8 / 16 page ADM8690–ADM8695 REV. 0 –8– (PFI) is compared to an internal +1.3 V reference. The Power Fail Output ( PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider that senses either the unregulated dc input to the system’s 5 V regu- lator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.3 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut down procedure executed before power is lost ADM869x 1.3V POWER FAIL OUTPUT POWER FAIL INPUT PFO R1 R2 INPUT POWER Figure 7. Power Fail Comparator Table II. Input and Output Status In Battery Backup Mode Signal Status VOUT VOUT is connected to VBATT via an internal PMOS switch. RESET Logic low. RESET Logic high. The open circuit output voltage is equal to VOUT. LOW LINE Logic low. BATT ON Logic high. The open circuit voltage is equal to VOUT. WDI WDI is ignored. It is internally disconnected from the internal pull-up resistor and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. WDO Logic high. The open circuit voltage is equal to VOUT. PFI The Power Fail Comparator is turned off and has no effect on the Power Fail Output. PFO Logic low. CEIN CEIN is ignored. It is internally disconnected from its internal pull-up and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. CEOUT Logic high. The open circuit voltage is equal to VOUT. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. CE Gating and RAM Write Protection (ADM8691/ADM8693/ ADM8695) The ADM8691/ADM8693/ADM8695 products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when VCC is at an in- valid level. There are two additional pins, CEIN and CEOUT, which may be used to control the Chip Enable or Write inputs of CMOS RAM. When VCC is present, CEOUT is a buffered rep- lica of CEIN, with a 3 ns propagation delay. When VCC falls be- low the reset voltage threshold or VBATT, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS or write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an in- valid level. Similar protection of EEPROMs can be achieved by using the CEOUT to drive the store or write inputs. ADM869x CEIN CEOUT VCC LOW = 0 VCC OK = 1 Figure 5. Chip Enable Gating VCC RESET LOW LINE t1 t1 t1 = RESET TIME V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 V1 V2 V2 V1 CEIN CEOUT Figure 6. Chip Enable Timing Power Fail Warning Comparator An additional comparator is provided for early warning of fail- ure in the microprocessor’s power supply. The Power Fail Input |
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