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ADP3088 Datasheet(PDF) 4 Page - Analog Devices |
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ADP3088 Datasheet(HTML) 4 Page - Analog Devices |
4 / 11 page ADP3088 –4– REV. PrK PRELIMINARY TECHNICAL DATA THEORY OF OPERATION The ADP3088 is a fixed frequency buck switching regula- tor in an MSOP-8 package using an external Schottky recti- fier. It features an integrated 1A power switch and switches at 1MHz. ADP3088 utilizes PWM operation and incorpo- rates soft-start for controlled start-up sequence and over temperature switch protection. The ADP3088 draws low current while running in power saving mode, and even lower current in shutdown. Refer to the functional block diagram on page 1. The sys- tem shown is configured for a 1.8 V output using a 10 µH inductor. At the beginning of a cycle the 1 MHz oscillator enables an SR latch, enabling the internal 1 A power switch. The current sense amplifier and the protection logic block monitor the current flowing between the IN and SW pins. The switch is turned off when the current reaches a level determined by the protection logic block or PWM comparator, whichever is lower. The error amplifier mea- sures the output voltage through an external resistor divider tied to the FB pin. This amplifier servos the switch current to regulate the FB pin voltage to 1.245 V. An internal regu- lator provides power to the control circuitry. The COMP pin can be used to shutdown the ADP3088. When pulled low it turns off the internal regulator, thus biasing down the chip, reducing the input current and disconnecting the output from the input. Anti-saturation circuitry is used to drive the switch to the edge of saturation. This allows the driver to quickly switch at 1 MHz and maintain good effi- ciency. And for improved efficiency, the DRV pin may be connected to the output provided that the input voltage is at least 1 V greater than the output. If the output load increases, the error amplifier will detect a lower voltage on the FB pin, via the resistor divider on the output, and send a signal to the PWM comparator to in- crease the on time of the switch. This in effect increases the duty cycle and provides more current to drive the increased load during the transient event, until a new operating point is established. Reference The ADP3088 incorporates an internal bandgap reference, it includes curvature correction for extremely low tempera- ture coefficient. The reference can be disabled by ground- ing the COMP pin which also turns off the bias for the rest of the chip. Error Amplifier The error amplifier provides a control voltage to the PWM stage to set the peak inductor current which sets the output current of the regulator. It is a gm amplifier in that its output is a current to the COMP pin. Protection Logic The protection logic block provides current limit and over- temperature protection. The over temperature protection is enabled when the temperature of the chip exceeds a speci- fied preset temperature; the switch will be disabled until the temperature drops below a specified level, then normal operation will resume. The thermal shutdown only stops switching, but does not put the chip to power saving mode, nor does it re-initiate soft start. As the chip cools slightly, it will cycle in and out of thermal shutdown rapidly, maintain- ing the die temp at 150°C, but allowing the output voltage and current to swing up and down. The current limit pro- tection overrides the PWM comparator; if this occurs then the switch pulse will be terminated and the soft start mode will be reset. Current Sense Amplifier The voltage on the internal current sense resistor is sensed and passed to the ramp input of the PWM comparator. This current sense signal is also passed to the current limit comparator for peak current limit shutdown . At current limit the soft-start capacitor is reset and soft-start is re- initiated. The current limit is normally 1.2 peak switch current. Slope compensation is added to ADP3088 to sta- bilize the loop. A generated ramped signal is summed with the current sense signal to provide slope compensation. Slope compensation is needed to close the inner loop so subharmonic oscillation is avoided. The ramp is reset with each clock cycle so that the ADP3088 is capable of true 100% duty cycle. Run/Stop Comparators This block creates the 1 MHz signal sent to the SR latch which is used for the switching frequency. It also takes the FB voltage and decides when to go into and wake up from power saving mode. The decision to induce power saving mode is based upon duty ratio. During steady-state con- tinuous operation, the duty ratio of a PWM buck regulator is simply a function of input/output voltage ratio, with sec- ond order effects including the voltage drop of the internal switch and the external diode. Once the load drops to a certain point, discontinuous operation occurs, and the duty ratio begins to modulate to maintain regulation. In the ADP3088, the regulator goes to sleep when the integrated duty ratio measurements drops to less than half of the mini- mum expected integrated duty ratio. The minimum ex- pected duty ratio occurs at max input voltage, min output voltage in continuous mode operation. PWM Comparator The PWM comparator looks at the signal from the current sense amplifier and the error amplifier to determine the correct switch on time to regulate the output voltage under a given load. Soft-Start Timer Soft start will prevent saturating the inductor which could cause uncontrolled overshoot of the output voltage and electrical stress to the system at start up. When first pow- ered up, an internal soft start capacitor is discharged and the soft start circuitry provides a gradually decaying offset to the error amplifier to prevent it from saturating and from commanding maximum switch current to charge the output capacitor. The output voltage approaches the final regula- tion voltage with a smooth exponential decay. This will reduce electrical stress to the system. Output The output stage contains the bipolar power switch, and the circuits necessary to switch it on and off quickly. The pass switch is driven to the edge of saturation and the result is a fast switching response and low switch resistance. For improved efficiency, the DRV pin may be connected to the output provided that the input voltage is at least 1 V higher than the output. This will send the current needed to drive the bipolar switch to the output load instead of routing it to |
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