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ADP3203JRU-085-RL Datasheet(PDF) 9 Page - Analog Devices |
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ADP3203JRU-085-RL Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page ADP3203 REV. PrD –9– PRELIMINARY TECHNICAL DATA THEORY OF OPERATION Overview Featuring a new proprietary single-or-dual-channel buck converter hysteretic control architecture developed by Analog Devices, Inc., the ADP3203 is the optimal core voltage control solution for both IMVP-II & -III generation microprocessors. The complex multi-tiered regulation requirements of either IMVP specification are easily implemented with the highly integrated functionality of this controller. Power Conversion Control Architecture Driving of the individual channels is accomplished using external drivers, such as the ADP3415. One PWM interface pin per channel, OUT1 and OUT2, is provided. A separate pin, DRVLSD, commands the driver to enable or disable synchro- nous operation during the off time of each channel. The same DRVLSD pin is connected to both drivers. The ADP3203 utilizes hysteretic control. The resistor from the HYSSET pin to ground sets up a current that is switched bi- directionally into a resistor interconnected between RAMP and CS+ pins. The switching of this current sets the hysteresis. In its dual-channel configuration, the hysteretic control requires multiplexing information in the two channels. The inductor current of the channel that is driven high is controlled against the upper hysteresis limit. During the common off-time of the two channels, the inductor currents are averaged together and compared against the lower hysteresis limit. This proprietary off-time averaging technique serves to eliminate a systematic offset that otherwise appears in a fully multiplexed hysteretic control system. Compensation As with all ADI products for core voltage control, the controller is compatible with ADOPT™ compensation, which provides the optimum output voltage containment within a specified voltage window or along a specified load-line using the fewest possible number of output capacitors. The inductor ripple current is kept at a fixed programmable value while the output voltage is regulated with fully programmable voltage positioning parameters, which can be tuned to optimize the design for any particular CPU regulation specifications. By controlling the ripple current rather than ripple voltage, the frequency varia- tions associated with changes in output impedance for standard ripple regulators will not appear. Feedback/Current Sensing Accurate current sensing is needed to accomplish output voltage positioning accurately, which, in turn, is required to allow the minimum number of output capacitors to be used to contain transients. A current sense resistor is used between each inductor and the output capacitors. To allow the control to operate without amplifiers, the negative feedback signal is multiplexed from the inductor, or upstream, side of the current sense resistors, and a positive feedback signal, if needed for load-line tuning is taken from the output, or downstream, side. Output Voltage Programming by VID, Offsets, & Load-Line In the IMVP-II & -III specifications, the output voltage is a function of both the core current – according to a specified load line – and the system operating mode – i.e., performance or battery optimized, normal or deepsleep clocking state, or deepersleep. The VID code programs the “nominal” core voltage. The core voltage decreases as a function of load current along the load line (which is synonymous with an output resistance of the power converter). The core voltage is also offset by a DC value – usually specified as a percentage – depending on the operating mode. The voltage offset is also called a “shift”. Two pins, BSHIFT and DSHIFT, are used to program the magnitude of the voltage shifts. The voltage shifts are accom- plished by injecting current at the node of the negative input pin of the feedback comparator. Resistive termination at the pins determines the magnitude of the voltage shifts. Two other pins, BOM and DSLP, are used to activate the respective two shifts only in their active low states. In the ADP3203, the shifts are mutually exclusive, with the DeepSleep shift (controlled by DSLP and DSHIFT pins) being the dominant one. Another pin, DPRSLP, eliminates both shifts only in its active high state. Its assertion corresponds to the DeeperSleep operating mode. Current Limiting The current programmed at the HYSSET pin and a resistor from the CS- pin to the common node of the current sense resistors sets the current limit. If the current limit threshold is triggered, a hysteresis is applied to the threshold so that hysteretic control is maintained during a current limited operating mode. Softstart and Hiccup A capacitor from the SS pin to determines both the soft-start time and the frequency at which hiccup will occur under a continuous short circuit or overload. System Signal Interface Several pins of the ADP3203 are meant to connect directly to system signals. The VID pins connect to the system VID control signals. The DPRSLP pin connects to the system’s DPRSLPVR signal. The DSLP pin connects to the system’s DPSLP or STPCPU signal. The BOM signal connects to the system’s GMUXSEL signal. In an IMVP-II system, the GMUXSEL signal preceeds any VID code change with a few nanoseconds, while in an IMVP-III system, it follows it with a maximum 12 µs delay. To comply with both specifications, the ADP3203 has a VID register in front of the DAC inputs that is written by a short pulse generated at the rising or falling edge of the GMUSEL signal. In an IMVP-II configuration, if the external VID multiplex settling time is longer than the internal VID register's write pulse-width, then the insertion of an external RC delay network in the GMUXSEL signal path (in front of the BOM pin) is recommended. The Intel spec calls for maximum 200 ns VID code set-up time. This specification can be met with a simple RC network which consists of only a 220 k Ω resistor, and no external capacitor just the BOM pin's capacitance. Undervoltage Lockout The ADP3203’s supply pin, V CC, has undervoltage lockout (UVLO) functionality to ensure that if V CC is too low to maintain proper operation, the IC will remain off and in a low current state. |
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