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ADSP-2171BS-133 Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-2171BS-133 Datasheet(HTML) 2 Page - Analog Devices |
2 / 52 page REV. A –2– ADSP-2171/ADSP-2172/ADSP-2173 Development System The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-217x. The System Builder provides a high-level method for defining the architecture of systems under develop- ment. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation’s GNU C Compiler, generates ADSP-217x assembly source code. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. EZ-Tools, low cost, easy-to-use hardware tools, also support the ADSP-217x. The ADSP-217x EZ-ICE ® Emulator aids in the hardware de- bugging of ADSP-217x systems. The emulator consists of hard- ware, host computer resident software, the emulator probe, and the pin adaptor. The emulator performs a full range of emula- tion functions including stand-alone operation or operation in the target, setting up to 20 breakpoints, single-step or full-speed operation in the target, examining and altering registers and memory values, and PC upload/download functions. If you plan to use the emulator, you should consider the emulator’s restric- tions (differences between emulator and processor operation). The EZ-LAB ® Evaluation Board is a PC plug-in card, but it can operate in stand-alone mode. The evaluation board/system de- velopment board executes EPROM-based or downloaded pro- grams. Modular Analog Front End daughter cards with different codecs will be made available. EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc. Additional Information This data sheet provides a general overview of ADSP-217x functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual. For more information about the Development System and ADSP-217x programmer’s reference information, refer to the ADSP-2100 Family Assembler Tools & Simulator Manual. ARCHITECTURE OVERVIEW Figure 1 is an overall block diagram of the ADSP-217x. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations. The ALU per- forms a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. The sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-217x executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. Figure 1. ADSP-217x Block Diagram R BUS 16 HIP CONTROL HIP REGISTERS BOOT ADDRESS GENERATOR BUS EXCHANGE COMPANDING CIRCUITRY DMA BUS PMA BUS DMD BUS PMD BUS PROGRAM SEQUENCER INSTRUCTION REGISTER DATA ADDRESS GENERATOR #2 DATA ADDRESS GENERATOR #1 14 14 INPUT REGS OUTPUT REGS SHIFTER INPUT REGS OUTPUT REGS MAC INPUT REGS OUTPUT REGS ALU 24 16 5 16 MUX 24 MUX SERIAL PORT 0 RECEIVE REG TRANSMIT REG CONTROL LOGIC DATA SRAM 2K X 16 POWER DOWN CONTROL LOGIC 14 TIMER 2 3 11 HIP DATA BUS PROGRAM ROM 8K X 24 PROGRAM SRAM 2K X 24 SERIAL PORT 1 RECEIVE REG TRANSMIT REG FLAGS EXTERNAL DATA BUS EXTERNAL ADDRESS BUS 5 |
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