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ADSP-2187LKST-210 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-2187LKST-210 Datasheet(HTML) 1 Page - Analog Devices |
1 / 32 page a DSP Microcomputer ADSP-2187L REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ICE-Port is a trademark of Analog Devices, Inc. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 GENERAL NOTE This data sheet represents specifications for the ADSP-2187L 3.3 V processor. GENERAL DESCRIPTION The ADSP-2187L is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2187L combines the ADSP-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2187L integrates 160K bytes of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also pro- vided to meet the low power needs of battery operated portable equipment. The ADSP-2187L is available in 100-lead TQFP package. In addition, the ADSP-2187L supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking, for increased flexibility. Fabricated in a high speed, low power, CMOS process, the ADSP-2187L operates with a 19 ns instruction cycle time. Ev- ery instruction can execute in a single processor cycle. FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 160K Bytes of On-Chip RAM, Configured as 32K Words Program Memory RAM and 32K Words Data Memory RAM Dual Purpose Program Memory for Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port™ Emulator Interface Supports Debugging in Final Systems FUNCTIONAL BLOCK DIAGRAM SERIAL PORTS SPORT 1 SPORT 0 MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER 32K 24 PM 8K 24 OVERLAY 1 8K 24 OVERLAY 2 TIMER ADSP-2100 BASE ARCHITECTURE SHIFTER MAC ALU ARITHMETIC UNITS POWER-DOWN CONTROL PROGRAM SEQUENCER DAG 2 DAG 1 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS INTERNAL DMA PORT EXTERNAL DATA BUS OR FULL MEMORY MODE HOST MODE 32K 16 DM 8K 16 OVERLAY 1 8K 16 OVERLAY 2 () () |
Número de pieza similar - ADSP-2187LKST-210 |
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Descripción similar - ADSP-2187LKST-210 |
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