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ADSP-2195MKST-160X Datasheet(PDF) 3 Page - Analog Devices

No. de pieza ADSP-2195MKST-160X
Descripción Electrónicos  DSP Microcomputer
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ADSP-2195MKST-160X Datasheet(HTML) 3 Page - Analog Devices

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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2195
September 2001
35(/,0,1$5< 7(&+1,&$/ '$7$
TABLE OF CONTENTS
ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . 1
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 4
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . . 5
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . 6
Internal On-Chip ROM . . . . . . . . . . . . . . . . . . . . 6
On-Chip Memory Security . . . . . . . . . . . . . . . . . 7
External (Off-Chip) Memory . . . . . . . . . . . . . . . . 8
External Memory Space . . . . . . . . . . . . . . . . . . . . 8
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . 8
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Host Port Acknowledge (HACK) Modes . . . . . . 10
Host Port Chip Selects . . . . . . . . . . . . . . . . . . . 11
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . 11
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . 11
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . 12
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 13
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down Core Mode . . . . . . . . . . . . . . . . . . 13
Power-Down Core/Peripherals Mode . . . . . . . . . 13
Power-Down All Mode . . . . . . . . . . . . . . . . . . . 13
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . 16
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 16
Designing an Emulator-Compatible DSP Board
(Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Target Board Header . . . . . . . . . . . . . . . . . . . . . 17
JTAG Emulator Pod Connector . . . . . . . . . . . . 18
Design-for-Emulation Circuit Information . . . . . 18
Additional Information . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended Operating Conditions
. . . . . . . . . . 22
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . 22
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 24
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 24
Clock In and Clock Out Cycle Timing . . . . . . . 25
Programmable Flags Cycle Timing . . . . . . . . . . 26
Timer PWM_OUT Cycle Timing . . . . . . . . . . . 27
External Port Write Cycle Timing . . . . . . . . . . . 28
External Port Read Cycle Timing . . . . . . . . . . . 30
External Port Bus Request and Grant Cycle
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Host Port ALE Mode Write Cycle Timing . . . . 34
Host Port ACC Mode Write Cycle Timing . . . . 36
Host Port ALE Mode Read Cycle Timing . . . . . 38
Host Port ACC Mode Read Cycle Timing . . . . 40
Serial Port (SPORT) Clocks and Data Timing . 42
Serial Port (SPORT) Frame Synch Timing . . . . 44
Serial Peripheral Interface (SPI) Port—Master
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Serial Peripheral Interface (SPI) Port—Slave
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
JTAG Test And Emulation Port Timing . . . . . . 51
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 52
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Output Disable Time . . . . . . . . . . . . . . . . . . . . 54
Output Enable Time . . . . . . . . . . . . . . . . . . . . . 54
Example System Hold Time Calculation . . . . . . 55
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . 55
Environmental Conditions . . . . . . . . . . . . . . . . . . . . 55
Thermal Characteristics . . . . . . . . . . . . . . . . . . 55
ADSP-2195 144-Lead LQFP Pinout . . . . . . . . . . . . 58
ADSP-2195 144-Lead Mini-BGA Pinout . . . . . . . . 67
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68


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