ADS54T01

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SLAS918 – DECEMBER 2012

ELECTRICAL CHARACTERISTICS

clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

OVER-DRIVE RECOVERY ERROR

Recovery to within 5% (of final value) for 6dB

Input overload recovery

2

ns

overload with sine wave input

SAMPLE TIMING CHARACTERISTICS

rms

Aperture Jitter

Sample uncertainty

100

fs rms

ADC sample to digital output, Auto correction

38

disabled

Clock

Cycles

ADC sample to digital output, Auto correction

50

Data Latency

enabled

Sampling

ADC sample to digital output, Decimation filter

74

clock

enabled, Auto correction disabled

Cycles

Clock

Over-range Latency

ADC sample to over-range output

12

Cycles

ELECTRICAL CHARACTERISTICS

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE

0.7 x

High-level input voltage

V

IOVDD

All digital inputs support 1.8V and 3.3V logic

levels.

0.3 x

Low-level input voltage

V

IOVDD

High-level input current

–50

200

µA

Low-level input current

–50

50

µA

Input capacitance

5

pF

DIGITAL OUTPUTS – SDO

IOVDD –

Iload = -100uA

0.2

High-level output voltage

V

0.8 x

Iload = -2mA

IOVDD

Iload = 100uA

0.2

Low-level output voltage

V

0.22 x

Iload = 2mA

IOVDD

DIGITAL INPUTS – SYNCP/N, TRIGGERP/N

Differential input voltage

250

350

450

mV

Input common mode voltage

1.125

1.2

1.375

V

500

ps

DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N

Output differential voltage

Iout = 3.5mA

250

350

450

mV

Output common mode voltage

Iout = 3.5mA

1.125

1.25

1.375

V

Data valid to zero-crossing of DACLK

320

400

ps

Zero-crossing of DACLK to data becoming

250

320

ps

invalid

CLKIN falling edge to DACLK rising edge

3.36

3.69

3.92

ns

10% - 90%

100

150

200

ps

90% - 10%

100

150

200

ps

Copyright © 2012, Texas Instruments Incorporated

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