ADS54T02

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SLAS933 – JANUARY 2013

PACKAGE/ORDERING INFORMATION

SPECIFIED

LEAD/

TRANSPORT

ECO

ORDERING

PACKAGE-

PACKAGE

PACKAGE

PRODUCT

TEMPERATURE

BALL

MEDIA,

LEAD

DESIGNATOR

MARKING

NUMBER

RANGE

FINISH

QUANTITY

GREEN

ADS54T02IZAY

Tray

ADS54T02

196-BGA

ZAY

–40°C to 85°C

ADS54T02I

(RoHS & no

ADS54T02IZAYR

Tape and Reel

Sb/Br)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

Supply voltage range, AVDD33

–0.5

4

V

Supply voltage range, AVDDC

–0.5

2.3

V

Supply voltage range, AVDD18

–0.5

2.3

V

Supply voltage range, DVDD

–0.5

2.3

V

Supply voltage range, DVDDLVDS

–0.5

2.3

V

Supply voltage range, IOVDD

–0.5

4

V

INA/B_P, INA/B_N

–0.5

AVDD33 + 0.5

V

CLKINP, CLKINN

–0.5

AVDDC + 0.5

V

Voltage applied to input pins

SYNCP, SYNCN

–0.5

AVDD33 + 0.5

V

SRESET, SDENB, SCLK, SDIO, SDO, ENABLE

–0.5

IOVDD + 0.5

V

–40

85

°C

150

°C

Storage temperature range

–65

150

°C

ESD, Human Body Model

2

kV

THERMAL INFORMATION

ADS54T02

QFN

UNITS

196 PINS

37.6

6.8

16.8

°C/W

0.2

16.4

N/A

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(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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