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ADS61JB23IRHAR Datasheet(PDF) 2 Page - Texas Instruments |
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ADS61JB23IRHAR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 45 page REFERENCE CONTROL INTERFACE INP INM VCM ADC_OUTP<0> ADC_OUTM<0> OVR CML OUTPUTS CLOCKGEN 12 bit ADC JESD204A Digital PLL 10X/20X Buffer ADC_OUTP<1> ADC_OUTM<1> Signal level detect DETECT<3:0> CMOS OUTPUTS ADS61JB23 SLOS755 – DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS61JB23 |
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