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ADS5401 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS5401 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 40 page  A B C D E F G H J K L M N P 14 VREF VCM GND INB_N INB_P GND AVDDC AVDDC GND INA_P INA_N GND GND CLKINP 14 13 SDENB TEST MODE GND GND GND GND GND GND GND GND GND GND GND CLKINN 13 12 SCLK SRESET B GND AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 GND AVDD33 AVDD33 12 11 SDIO ENABLE GND AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 GND AVDD18 AVDD18 11 10 SDO IOVDD GND AVDD18 GND GND GND GND GND GND AVDD18 GND NC NC 10 9 DVDD DVDD GND GND GND GND GND GND GND GND GND GND SYNCN SYNCP 9 8 DVDD DVDD DVDD DVDD GND GND GND GND GND GND DVDD DVDD DVDD DVDD 8 7 DB0N DB0P DVDD LVDS DVDD LVDS GND GND GND GND GND GND DVDD LVDS DVDD LVDS NC NC 7 6 DB1N DB1P DVDD LVDS DVDD LVDS GND GND GND GND GND GND DVDD LVDS DVDD LVDS NC NC 6 5 DB2N DB2P OVRBN OVRBP GND GND GND GND GND GND OVRAN OVRAP SYNC OUTN SYNC OUTP 5 4 DB3N DB3P DB8P DB10P NC NC NC DA0P DA2P DA4P DA6P DA8P NC NC 4 3 DB4N DB4P DB8N DB10N NC NC NC DA0N DA2N DA4N DA6N DA8N DA11N DA11P 3 2 DB5N DB5P DB7P DB9P DB11P SYNC OUTP DBCLKP DACLKP DA1P DA3P DA5P DA7P DA10N DA10P 2 1 DB6N DB6P DB7N DB9N DB11N SYNC OUTN DBCLKN DACLKN DA1N DA3N DA5N DA7N DA9N DA9P 1 A B C D E F G H J K L M N P ADS5402 www.ti.com SLAS936 – MARCH 2013 PINOUT INFORMATION Figure 2. Pinout in DDR output mode (top down view) PIN ASSIGNMENTS PIN I/O DESCRIPTION NAME NUMBER INPUT/REFERENCE INA_P/N K14, L14 I Analog ADC A differential input signal. INB_P/N D14, E14 I Analog ADC B differential input signal. Output of the analog input common mode (nominally 1.9V). A 0.1 μF capacitor to AGND is VCM B14 O recommended. Reference voltage output (2V nominal). A 0.1 μF capacitor to AGND is recommended, but not VREF A14 O required. CLOCK/SYNC CLKINP/N P14, P13 I Differential input clock Synchronization input. Inactive if logic low. When clocked in a high state initially, this is used SYNCP/N P9, N9 I for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100 Ω termination. CONTROL/SERIAL Serial interface reset input. Active low. Initialized internal registers during high to low SRESET B12 I transition. Asynchronous. Internal 50k Ω pull up resistor to IOVDD. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADS5402 |
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