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ACTF512K8 Datasheet(PDF) 5 Page - Aeroflex Circuit Technology

No. de Pieza. ACTF512K8
Descripción  ACT-F512K8 High Speed 4 Megabit Monolithic FLASH
Descarga  21 Pages
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Fabricante  AEROFLEX [Aeroflex Circuit Technology]
Página de inicio  http://www.aeroflex.com
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ACTF512K8 Datasheet(HTML) 5 Page - Aeroflex Circuit Technology

 
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Aeroflex Circuit Technology
SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
5
Device Operation
The ACT–F512K8 Monolithic is composed of One, Four
megabit flash device. Programming of the ACT–F512K8
is accomplished by executing the program command
sequence. The program algorithm, which is an internal
algorithm, automatically times the program pulse widths
and verifies proper cell status.
Sectors can be pro-
gramed and verified in less than 1 second.
Erase is
accomplished
by
executing
the
erase
command
sequence. The erase algorithm, which is internal, auto-
matically preprograms the array if it is not already pro-
gramed before executing the erase operation.
During
erase, the device automatically times the erase pulse
widths and verifies proper cell status. The entire mem-
ory is typically erased and verified in 1.5 seconds (if
pre-programmed). The sector mode allows for 64K byte
blocks of memory to be erased and reprogrammed with-
out affecting other blocks.
Bus Operation
READ
The ACT–F512K8 has two control functions, both of
which must be logically active, to obtain data at the out-
puts. Chip Enable (CE) is the power control and should
be used for device selection. Output-Enable (OE) is the
output control and should be used to gate data to the
output pins of the chip selected. Figure 7 illustrates AC
read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output
from the device is disabled. Output pins are placed in a
high impedance state.
STANDBY MODE
The ACT-F512K8 standby mode consumes less than 6.5
mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input. If the
device is deselected during erasure or programming, the
device will draw active current until the operation is com-
pleted.
WRITE
Device erasure and programming are accomplished via
the command register.
The contents of the register
serve as input to the internal state machine. The state
machine outputs dictate the function of the device.
The command register itself does not occupy an addres-
sable memory location. The register is a latch used to
store the command, along with address and data infor-
mation needed to execute the command. The command
register is written by bringing WE to a logic low level
(VIL), while CE is low and OE is at VIH. Addresses are
latched on the falling edge of WE or CE, whichever hap-
pens later. Data is latched on the rising edge of the WE
or CE whichever occurs first. Standard microprocessor
write timings are used. Refer to AC Program Character-
istics and Waveforms, Figures 3, 8 and 13.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command regis-
ter. Microprocessor read cycles retrieve array data from
the memory. The device remains enabled for reads until
the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a com-
mand sequence is not required to read data. Standard
Microprocessor read cycles will retrieve array data. This
default value ensures that no spurious alteration of the
memory content occurs during the power transition.
Refer to the AC Read Characteristics and Figure 7 for
the specific timing parameters.
BYTE PROGRAMING
The device is programmed on a byte-byte basis. Pro-
gramming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program
Table 1 – Bus Operations
Operation
CE OE WE A0 A1 A9
I/O
READ
L
L
H
A0
A1
A9
DOUT
STANDBY
H
X
X
X
X
X
HIGH Z
OUTPUT DISABLE
L
H
H
X
X
X
HIGH Z
WRITE
L
H
L
A0
A1
A9
DIN
ENABLE SECTOR
PROTECT
L
VID
L
X
X
VID
X
VERIFY SECTOR
PROTECT
L
L
H
L
H
VID
Code
Table 2 – Sector Addresses Table
A16 A15
A14
Address Range
SA0
0
0
0
00000h – 03FFFh
SA1
0
0
1
04000h – 07FFFh
SA2
0
1
0
08000h – 0BFFFh
SA3
0
1
1
0C000h – 0FFFFh
SA4
1
0
0
10000h – 13FFFh
SA5
1
0
1
14000h – 17FFFh
SA6
1
1
0
18000h – 1BFFFh
SA7
1
1
1
1C000h – 1FFFFh


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