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ACTF512K8 Datasheet(PDF) 6 Page - Aeroflex Circuit Technology

No. de Pieza. ACTF512K8
Descripción  ACT-F512K8 High Speed 4 Megabit Monolithic FLASH
Descarga  21 Pages
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Fabricante  AEROFLEX [Aeroflex Circuit Technology]
Página de inicio  http://www.aeroflex.com
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ACTF512K8 Datasheet(HTML) 6 Page - Aeroflex Circuit Technology

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Aeroflex Circuit Technology
SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
6
set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever
occurs later, while the data is latched on the rising edge
of CE or WE whichever occurs first. The rising edge of
CE or WE begins programming. Upon executing the pro-
gram algorithm command sequence the system is not
required to provide further controls or timings.
The
device will automatically provide adequate internally
generated program pulses and verity the programmed
cell status.
The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched. The
device requires a valid address be supplied by the Sys-
tem at this time. Data Polling must be performed at the
memory location which is being programmed.
Programming is allowed in any address sequence and
across sector boundaries.
Figure 3 illustrates the programming algorithm using typ-
ical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
'unlock' write cycles. These are followed by writing the
'set-up' command. Two more 'unlock' write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
device prior to erase. Upon executing the erase algo-
rithm (Figure 4) sequence the device automatically will
program and verify the entire memory for an all zero data
pattern prior to electrical erase.
The system is not
required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to read
the mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
100µs from the rising edge of the last sector erase com-
mand will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase com-
mand 30H to address in other sectors desired to be con-
currently erased.
A time-out of 100µs from the rising
edge of the WE pulse for the last sector erase command
will initiate the sector erase.
If another sector erase
command is written within the 100µs time-out window
the timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 7).
Sector erase does not require the user to program the
device prior to erase.
The device automatically pro-
grams all memory locations in the sector(s) to be erased
prior to electrical erase. When erasing a sector or sec-
tors the remaining unselected sectors are not affected.
The system is not required to provide any controls or tim-
ings during these operations.
Data Protection
The ACT–F512K8 is designed to offer protection against
accidental erasure or programming caused by spurious
system level singles that may exist during power transi-
tions. During power up the device automatically resets
the internal state machine in the read mode. Also, with
Table 3 — Commands Definitions
Command
Sequence
Bus
Write
Cycles
First Bus Write
Cycle
Second Bus Write
Cycle
Third Bus Write
Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus Write
Cycle
Sixth Bus Write
Cycle
Required
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read/Reset
1
XXXH
F0H
Read/Reset
4
5555H
AAH
2AAAH
55H
5555H
F0H
RA
RD
Autoselect
4
5555H
AAH
2AAAH
55H
5555H
90H
Byte Program
6
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD
Chip Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.


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