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BDP1A16G Datasheet(PDF) 9 Page - Agere Systems |
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BDP1A16G Datasheet(HTML) 9 Page - Agere Systems |
9 / 16 page Lucent Technologies Inc. 9 Data Sheet January 1999 BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA Quad Differential Drivers ESD Failure Models Lucent employs two models for ESD events that can cause device damage or failure. 1. A human-body model (HBM) that is used by most of the industry for ESD-susceptibility testing and protection-design evaluation. ESD voltage thresh- olds are dependent on the critical parameters used to define the model. A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. 2. A charged-device model (CDM), which many believe is the better simulator of electronics manu- facturing exposure. Tables 5 and 6 illustrate the role these two models play in the overall prevention of ESD damage. HBM ESD testing is intended to simulate an ESD event from a charged person. The CDM ESD testing simulates charging and discharging events that occur in produc- tion equipment and processes, e.g., an integrated cir- cuit sliding down a shipping tube. The HBM ESD threshold voltage presented here was obtained by using these circuit parameters. Table 5. Typical ESD Thresholds for Data Transmission Drivers Table 6. ESD Damage Protection Device HBM Threshold CDM Threshold BDG1A, BDGLA >2500 >1000 BDP1A >2500 >2000 BPPGA, BPNGA, BPNPA >3000 >2000 ESD Threat Controls Personnel Processes Control Wrist straps ESD shoes Antistatic flooring Static-dissipative materials Air ionization Model Human-body model (HBM) Charged-device model (CDM) Latch-Up Latch-up evaluation has been performed on the data transmission drivers. Latch-up testing determines if power- supply current exceeds the specified maximum due to the application of a stress to the device under test. A device is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that level after the stress is removed. Lucent performs latch-up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previ- ously JC-40.2) “CMOS Latch-Up Standardized Test Procedure.” Latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels: 1. dc current stressing of input and output pins. 2. Power supply slew rate. 3. Power supply overvoltage. Table 7. Latch-Up Test Criteria and Test Results Based on the results in Table 6, the data transmission drivers pass the Lucent latch-up testing requirements and are considered not susceptible to latch-up. dc Current Stress of I/O Pins Power Supply Slew Rate Power Supply Overvoltage Data Transmission Driver ICs Minimum Criteria ≥150 mA ≤1 µs ≥1.75 × Vmax Test Results ≥250 mA ≤100 ns ≥2.25 × Vmax |
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