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TDAT042G51A-3BLL1 Datasheet(PDF) 9 Page - Agere Systems |
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TDAT042G51A-3BLL1 Datasheet(HTML) 9 Page - Agere Systems |
9 / 310 page Agere Systems Inc. 7 Advisory May 2001 for Version 1 and 1A of the Device TDAT042G5 Device Advisory Path Terminator (PT) (continued) PT5. Delta/Event Registers in COR Mode Because there is a one-cycle delay before the PT delta event registers (0x802, 0x080F, 0x081C, 0x0829) are cleared after being read in COR mode, new interrupts may be lost. Workaround No workaround is available for this condition. Corrective Action This condition will be addressed in future versions of the device. Data Engine (DE) DE1. SDL Mode—Header Error Correction in LSB In SDL mode, the header error correction process is susceptible to single-bit errors in the least significant bit (LSB) of the special payload. Workaround No workaround is available for this condition. Corrective Action This condition will be addressed in future versions of the device. DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation Currently, the LCD is implemented in the same way that out of cell delineation (OCD) is implemented. This is not in accordance with the ITU-TI.432-2 February 1999 standard. Workaround No workaround is available for this condition. Corrective Action A software workaround will be available with version 1A of the device. |
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