ADV7182WBCPZ-RL datasheet(10/96 Pages) AD

No. de pieza	ADV7182WBCPZ-RL

Descripción Electrónicos	10-Bit, SDTV Video Decoder with Differential Inputs

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ADV7182

Data Sheet

Rev. A | Page 10 of 96

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1, 4

DGND

G

Ground for Digital Supply.

2

DVDDIO

P

Digital I/O Supply Voltage (1.8 V to 3.3 V).

3, 13

DVDD

P

Digital Supply Voltage (1.8 V).

5 to 12

P7 to P0

O

Video Pixel Output Port.

14

XTALP

O

This pin should be connected to the 28.6363 MHz crystal or not connected if an external

1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7182. In crystal mode, the

crystal must be a fundamental crystal.

15

XTALN

I

Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,

28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

16

PVDD

P

PLL Supply Voltage (1.8 V).

17, 18, 22, 23

AIN1 to AIN4

I

Analog Video Input Channels.

19

VREFP

O

Internal Voltage Reference Output.

20

VREFN

O

Internal Voltage Reference Output.

21

AVDD

P

Analog Supply Voltage (1.8 V).

24

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video.

25

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7182 circuitry.

26

ALSB

I

This pin selects the I2C address for the ADV7182. For ALSB set to Logic 0, the address

selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.

27

SDATA

I/O

I2C Port Serial Data Input/Output Pin.

28

SCLK

I

I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

29

VS/FIELD/SFL

O

Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier

Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier

frequency when this decoder is connected to any Analog Devices digital video encoder.

30

HS

O

Horizontal Synchronization Output Signal.

31

PWRDWN

I

A logic low on this pin places the ADV7182 is in power-down mode.

32

LLC

O

Line-Locked Output Clock for Output Pixel Data. Nominally 27 MHz but varies up or down

according to the video line length.

EPAD (EP)

The exposed pad must be connected to DGND.

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

24 INTRQ

23 AIN4

22 AIN3

21 AVDD

20 VREFN

19 VREFP

18 AIN2

17 AIN1

1

2

3

4

5

6

7

8

DGND

DVDDIO

DVDD

DGND

P7

P6

P5

P4

ADV7182

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