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Datasheet

Datasheet

BRCA016GWZ-W (16Kbit)

© 2013 ROHM Co., Ltd. All rights reserved.

www.rohm.com

25.Feb.2013 Rev.002

TSZ02201-0R2R0G100510-1-2

I/O Equivalence Circuit

1.

2.

Input / Output (SDA)

Power-Up / Down Conditions

At power on, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal

logic circuit not completely reset, hence, malfunction may occur. To prevent this,

the IC is equipped with POR circuit and

LVCC circuit. To assure the operation, observe the following conditions at power on.

1. Set SDA = 'H' and SCL ='L' or 'H'

3. Set SDA and SCL so as not to become 'Hi-Z'.

When the above conditions 1 and 2 cannot be observed, take the following countermeasures.

(1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power on.

→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.

(2) In the case when the above condition 2 cannot be observed.

→After power source becomes stable, execute software reset(Page 15).

(3) In the case when the above conditions 1 and 2 cannot be observed.

→Carry out (1), and then carry out (2).

Figure 42. Input Pin Circuit Diagram

Figure 43. Input / Output Pin Circuit Diagram

0

Figure 44. Rise Waveform Diagram

After Vcc becomes stable

SCL

SDA

After Vcc becomes stable

Figure 45. When SCL= 'H' and SDA= 'L'

Figure 46. When SCL='H' and SDA='L'

t

OFF

10ms or below

10ms or longer

0.3V or below

100ms or below

10ms or longer

0.2V or below