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74VCX162838 Datasheet(PDF) 1 Page - Fairchild Semiconductor

No. de Pieza. 74VCX162838
Descripción  Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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74VCX162838 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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© 2000 Fairchild Semiconductor Corporation
DS500045
www.fairchildsemi.com
August 1997
Revised July 2000
74VCX162838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
and 26
Ω Series Resistors in the Outputs
General Description
The VCX162838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through the use of the
OE pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.
The 74VCX162838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162838 is also designed with 26
Ω series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74VCX162838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26
Ω series resistors in the outputs
s tPD (CP to On)
3.9 ns max for 3.0V to 3.6V VCC
5.4 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±12 mA @ 3.0V V
CC
±8 mA @ 2.3V V
CC
±3 mA @ 1.65V V
CC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model
> 2000V
Machine model
> 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor. The minimum
value of the resistor is determined by the current -sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Ordering Code
Package Number
Package Descriptions
74VCX162838MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
CP
Clock Pulse Input
REGE
Register Enable Input


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