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74VHC240MTC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74VHC240MTC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 2005 Fairchild Semiconductor Corporation DS011506 www.fairchildsemi.com October 1992 Revised April 2005 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs General Description The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi- pation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD 3.6ns (typ) at TA 25qC s Low power dissipation: ICC 4 PA (max) @ TA 25qC s High noise immunity: VNIH VNIL 28% VCC (min) s Power down protection is provided on all inputs s Low noise: VOLP 0.9V (max) s Pin and function compatible with 74HC240 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol IEEE/IEC Connection Diagram Order Number Package Number Package Description 74VHC240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC240SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide |
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