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74VHC595SJX Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74VHC595SJX Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Pin Descriptions Truth Table Timing Diagram Pin Names Description SER Serial Data Input SCK Shift Register Clock Input (Active rising edge) RCK Storage Register Clock Input (Active rising edge) SCLR Reset Input G 3-STATE Output Enable Input (Active LOW) QA - QH Parallel Data Outputs Q’H Serial Data Output Inputs Function SER RCK SCK SCLR G XX X X H QA thru QH 3-STATE XX X X L QA thru QH outputs enabled X X X L L Shift Register cleared Q ′ H = 0 LX ↑ H L Shift Register clocked QN = Qn-1, Q0 = SER = L HX ↑ H L Shift Register clocked QN = Qn-1, Q0 = SER = H X ↑ X H L Contents of Shift Register transferred to output latches |
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