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ACE25C512 Datasheet(PDF) 5 Page - ACE Technology Co., LTD. |
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ACE25C512 Datasheet(HTML) 5 Page - ACE Technology Co., LTD. |
5 / 34 page ACE25C512 512K-BIT Serial Flash Memory VER 1.2 5 1 001000h 001FFFh 0 000000h 003FFFh Block (32KB) Sector (4KB) Address Range 1 15 00F000h 00FFFFh . . . . . . 9 009000h 009FFFh 8 008000h 008FFFh 0 7 007000h 007FFFh . . . . . . 1 001000h 001FFFh 0 000000h 003FFFh Table 1 Memory organization Device Operations Standard SPI The ACE25C512 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference betwe en Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#. Figure 2 The difference between Mode 0 and Mode 3 Dual SPI The ACE25C512 supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power -up (code-shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions, |
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