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CD4015BCM Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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CD4015BCM Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page October 1987 Revised January 1999 © 1999 Fairchild Semiconductor Corporation DS005948.prf www.fairchildsemi.com CD4015BC Dual 4-Bit Static Shift Register General Description The CD4015BC contains two identical, 4-stage, serial- input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the “Reset” input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS. Features s Wide supply voltage range: 3.0V to 18V s High noise immunity: 0.45 VDD (typ.) s Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS s Medium speed operation: 8 MHz (typ.) clock rate s Fully static design: @VDD − VSS = 10V Applications • Serial-input/parallel-output data queueing • Serial to parallel data conversion • General purpose register Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Truth Table X = Don't Care Case Note 1: Level Change Order Number Package Number Package Description CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CL (Note 1) DR Q1 Qn 00 0 Qn−1 10 1 Qn−1 X0 Q1 Qn (No change) XX 1 0 0 |
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