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CD4046BCM Datasheet(PDF) 1 Page - Fairchild Semiconductor

No. de Pieza. CD4046BCM
Descripción  Micropower Phase-Locked Loop
Descarga  14 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
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CD4046BCM Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 2002 Fairchild Semiconductor Corporation
October 1987
Revised March 2002
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) con-
sists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators. The two phase comparators have a common
signal input and a common comparator input. The signal
input can be directly coupled for a large voltage signal, or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digi-
tal error signal (phase comp. I Out) and maintains 90
phase shifts at the VCO center frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input frequencies that are close to har-
monics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase comp. II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0
° phase shift between signal
input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCOIN input, and the capacitor and resis-
tors connected to pin C1A, C1B, R1 and R2.
The source follower output of the VCOIN (demodulator Out)
is used with an external resistor of 10 k
Ω or more.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode is provided for power supply regulation, if
s Wide supply voltage range:
3.0V to 18V
s Low dynamic power consumption: 70
µW (typ.)
at fo = 10 kHz, VDD = 5V
s VCO frequency: 1.3 MHz (typ.) at VDD = 10V
s Low frequency drift: 0.06%/
°C at V
DD = 10V with
s High VCO linearity: 1% (typ.)
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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