© 2000 Fairchild Semiconductor Corporation

DS006413

www.fairchildsemi.com

August 1986

Revised March 2000

DM74LS245

3-STATE Octal Bus Transceiver

General Description

These octal bus transceivers are designed for asynchro-

nous two-way communication between data buses. The

control function implementation minimizes external timing

requirements.

The device allows data transmission from the A Bus to the

B Bus or from the B Bus to the A Bus depending upon the

logic level at the direction control (DIR) input. The enable

input (G) can be used to disable the device so that the

buses are effectively isolated.

Features

s Bi-Directional bus transceiver in a high-density 20-pin

package

s 3-STATE outputs drive bus lines directly

s PNP inputs reduce DC loading on bus lines

s Hysteresis at bus inputs improve noise margins

s Typical propagation delay times, port-to-port 8 ns

s Typical enable/disable times 17 ns

24 mA

−15 mA

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

H

= HIGH Level

L

= LOW Level

X

= Irrelevant

Order Number

Package Number

Package Description

DM74LS245WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS245SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS245N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Enable

Direction

Operation

G

Control

DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

HX

Isolation