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ADN4661 Datasheet(PDF) 10 Page - Analog Devices |
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ADN4661 Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AN-1177 Application Note Rev. 0 | Page 10 of 12 ISOLATION External interfaces can be isolated from logic circuits to prevent unwanted current flow that may damage or degrade the operation of electronic components. Galvanic isolation, shown in Figure 20, allows information flow, but prevents current flow. Complete isolation of data signals and power is possible using i Coupler® digital isolation and isoPower® power isolation. ISOLATOR POINT A POINT B ISOLATION BARRIER INFORMATION FLOW NO CURRENT FLOW PROTECT HUMANS/ EQUIPMENT ELIMINATE GROUNDING PROBLEMS IMPROVE SYSTEM PERFORMANCE Figure 20. Galvanic Isolation Allows Information Flow While Preventing Ground Current Flow Applications of isolation for LVDS and M-LVDS are safety isolation and/or functional isolation of board-to-board, back- plane, and PCB communication links. An example of safety isolation is a system with an M-LVDS backplane where one or more plug-in cards are at risk from high voltage transients. Isolating the M-LVDS interface ensures that such fault conditions do not affect other circuits in the system. An example of an application where functional isolation is beneficial is measurement equipment. Isolating LVDS links, for example, between an ADC and FPGA, can provide a floating ground plane to boost the integrity of measurement data, minimizing interference from the rest of the application. The circuit shown in Figure 21 is an isolated LVDS Interface Circuit from the Lab (CFTL), demonstrating complete isolation of an LVDS interface (see the References section). The ADuM3442 provides digital isolation of the logic inputs to the ADN4663 LVDS driver and the logic outputs from the ADN4664 LVDS receiver. Together with provision of isolated power using the ADuM5000, a number of challenges to isolating LVDS links in industrial and instrumentation applications are met that include the following: • Isolation of the logic signals to/from the LVDS drivers/ receivers, ensuring standard LVDS communication on the bus side of the circuit. • Highly integrated isolation using just two additional wide- body SOIC devices, the ADuM3442 and ADuM5000, to isolate the standard LVDS devices, the ADN4663 and ADN4664. • Low power consumption compared to traditional isolation (opto-couplers). • Multiple channels of isolation. This circuit demonstrates quad-channel isolation (in this case, two transmit and two receive channels). • High speed operation; the isolation can operate at up to 150 Mbps, facilitating basic LVDS speed requirements. The circuit shown in Figure 21 isolates a dual-channel LVDS line driver and a dual-channel LVDS receiver. This allows demonstration of two complete transmit and receive paths on a single board. OSC REC VISO VDD1 VDD1 VDD2 REG ADuM5000 3.3V ADuM3442 ISO 3.3V ISO 3.3V DIN1 DOUT1+ DOUT1– VCC ADN4663 DIN2 DOUT2+ DOUT2– LVDS BUS ADN4664 ROUT1 RIN1+ RIN1– VCC ROUT2 RIN2+ RIN2– ISO 3.3V FPGA ISOLATION BARRIER GND IN1 IN2 OUT1 OUT2 100Ω 100Ω R1 R2 Figure 21. Isolated LVDS Interface Circuit (Simplified Schematic, All Connections Not Shown) |
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