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AD8338ACPZ-RL Datasheet(PDF) 5 Page - Analog Devices |
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AD8338ACPZ-RL Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page Data Sheet AD8338 Rev. 0 | Page 5 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 INPR 2 INPD 3 INMD 4 INMR 11 OUTP 12 FBKP 10 OUTM 9 FBKM AD8338 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Pad. The exposed pad should be tied to a quiet analog ground. 1 INPR Positive 500 Ω Resistor Input for Voltage Input Applications. 2 INPD Positive Input for Current Input Applications. 3 INMD Negative Input for Current Input Applications. 4 INMR Negative 500 Ω Resistor Input for Voltage Input Applications. 5 COMM Ground. 6 MODE Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin. 7 GAIN Gain Control Input, 12.5 mV/dB or 80 dB/V. 8 DETO Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie this pin to COMM. 9 FBKM Negative Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section. 10 OUTM Negative Output. 11 OUTP Positive Output. 12 FBKP Positive Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section. 13 VAGC Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit. For more information, see the AGC Circuit section. 14 OFSN Offset Null Terminal. For more information, see the Offset Correction Circuit section. 15 VBAT Positive Supply Voltage. 16 VREF Internal 1.5 V Voltage Reference. |
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