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ADP5050 Datasheet(PDF) 5 Page - Analog Devices

No. de pieza ADP5050
Descripción Electrónicos  5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator
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ADP5050 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
ADP5050
Rev. 0 | Page 5 of 60
SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
VIN
4.5
15.0
V
PVIN1, PVIN2, PVIN3, PVIN4 pins
QUIESCENT CURRENT
PVIN1, PVIN2, PVIN3, PVIN4 pins
Operating Quiescent Current
IQ(4-BUCKS)
4.8
6.25
mA
No switching, all ENx pins high
ISHDN(4BUCKS+LDO)
25
65
µA
All ENx pins low
UNDERVOLTAGE LOCKOUT
UVLO
PVIN1, PVIN2, PVIN3, PVIN4 pins
Rising Threshold
VUVLO-RISING
4.2
4.36
V
Falling Threshold
VUVLO-FALLING
3.6
3.78
V
Hysteresis
VHYS
0.42
V
OSCILLATOR CIRCUIT
Switching Frequency
fSW
700
740
780
kHz
RT = 25.5 kΩ
Switching Frequency Range
250
1400
kHz
SYNC Input
Input Clock Range
fSYNC
250
1400
kHz
Input Clock Pulse Width
Minimum On Time
tSYNC_MIN_ON
100
ns
Minimum Off Time
tSYNC_MIN_OFF
100
ns
Input Clock High Voltage
VH(SYNC)
1.3
V
Input Clock Low Voltage
VL(SYNC)
0.4
V
SYNC Output
Clock Frequency
fCLK
fSW
kHz
Positive Pulse Duty Cycle
tCLK_PULSE_DUTY
50
%
Rise or Fall Time
tCLK_RISE_FALL
10
ns
High Level Voltage
VH(SYNC_OUT)
VVREG
V
PRECISION ENABLING
EN1, EN2, EN3, EN4, EN5 pins
High Level Threshold
VTH_H(EN)
0.806
0.832
V
Low Level Threshold
VTH_L(EN)
0.688
0.725
V
Pull-Down Resistor
RPULL-DOWN(EN)
1.0
MΩ
POWER GOOD
Internal Power-Good Rising Threshold
VPWRGD(RISE)
86.3
90.5
95
%
Internal Power-Good Hysteresis
VPWRGD(HYS)
3.3
%
Internal Power-Good Falling Delay
tPWRGD_FALL
50
µs
Rising Delay for PWRGD Pin
tPWRGD_PIN_RISE
1
ms
Leakage Current for PWRGD Pin
IPWRGD_LEAKAGE
0.1
1
µA
Output Low Voltage for PWRGD Pin
VPWRGD_LOW
50
100
mV
IPWRGD = 1 mA
LOGIC INPUTS (SCL AND SDA PINS)
VDDIO = 3.3 V
High Level Threshold
VLOGIC_HIGH
0.7 ×VDDIO
V
Low Level Threshold
VLOGIC_LOW
0.3 ×VDDIO
V
LOGIC OUTPUTS
Low Level Output Voltage
SDA Pin
VSDA_LOW
0.4
V
VDDIO = 3.3 V, ISDA = 3 mA
nINT Pin
VnINT_LOW
0.4
V
InINT = 3 mA
INTERNAL REGULATORS
VDD Output Voltage
VVDD
3.2
3.305
3.4
V
IVDD = 10 mA
VDD Current Limit
ILIM_VDD
20
51
80
mA
VREG Output Voltage
VVREG
4.9
5.1
5.3
V
VREG Dropout Voltage
VDROPOUT
225
mV
IVREG = 50 mA
VREG Current Limit
ILIM_VREG
50
95
140
mA


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