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AD5341BRUZ1 Datasheet(PDF) 5 Page - Analog Devices |
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AD5341BRUZ1 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 28 page  AD5330/AD5331/AD5340/AD5341 Rev. A | Page 5 of 28 TIMING CHARACTERISTICS1, 2, 3 VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Condition/Comments t1 0 ns min CS to WR setup time. t2 0 ns min CS to WR hold time. t3 20 ns min WR pulse width. t4 5 ns min Data, GAIN, BUF, HBEN setup time. t5 4.5 ns min Data, GAIN, BUF, HBEN hold time. t6 5 ns min Synchronous mode; WR falling to LDAC falling. t7 5 ns min Synchronous mode; LDAC falling to WR rising. t8 4.5 ns min Synchronous mode; WR rising to LDAC rising. t9 5 ns min Asynchronous mode; LDAC rising to WR rising. t10 4.5 ns min Asynchronous mode; WR rising to LDAC falling. t11 20 ns min LDAC pulse width. t12 20 ns min CLR pulse width. t13 50 ns min Time between WR cycles. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. CS WR DATA, GAIN, BUF, HBEN LDAC1 LDAC2 CLR NOTES: 1SYNCHRONOUS LDAC UPDATE MODE 2ASYNCHRONOUS LDAC UPDATE MODE t1 t2 t3 t4 t6 t7 t9 t10 t11 t12 t8 t5 t13 Figure 2. Parallel Interface Timing Diagram |
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