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AD9859 Datasheet(PDF) 7 Page - Analog Devices

No. de pieza AD9859
Descripción Electrónicos  400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD9859 Datasheet(HTML) 7 Page - Analog Devices

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AD9859
Rev. A | Page 7 of 24
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions—48-Lead TQFP/EP
Pin No.
Mnemonic
I/O
Description
1
I/O UPDATE
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This
pin must be set up and held around the SYNC_CLK output signal.
2, 34
DVDD
I
Digital Power Supply Pins (1.8 V).
3, 33, 42, 47,
48
DGND
I
Digital Power Ground Pins.
4, 6, 13, 16, 18,
19, 25, 27, 29
AVDD
I
Analog Power Supply Pins (1.8 V).
5, 7, 14, 15, 17,
22, 26, 28, 30,
31, 32
AGND
I
Analog Power Ground Pins.
8
OSC/
I
REFCLK
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-
ended mode, REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor.
9
OSC/REFCLK
I
Reference Clock/Oscillator Input. See the Clock Input section for details on the
OSCILLATOR/REFCLK operation.
10
CRYSTAL OUT
O
Output of the Oscillator Section.
11
CLKMODESELECT
I
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low,
the oscillator section is bypassed.
12
LOOP_FILTER
I
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 k Ω resistor in series with a 0.1 µF
capacitor tied to AVDD.
20
IOUT
O
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
21
IOUT
O
DAC Output. Should be biased through a resistor to AVDD, not AGND.
23
DACBP
I
DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
24
DAC_R
SET
I
A resistor (3.92 kΩ nominal) connected from AGND to DAC_R
SET establishes the reference
current for the DAC.
35
PWRDWNCTL
I
Input Pin Used as an External Power-Down Control (see Table 8 for details).
36
RESET
I
Active High Hardware Reset Pin. Asserting the RESET pin forces the AD9859 to the initial state,
as described in the I/O port register map.
37
IOSYNC
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC
is returned low. If unused, ground this pin; do not allow this pin to float.
38
SDO
O
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output.
When operated as a 2-wire serial port, this pin is unused and can be left unconnected.
39
CS
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
40
SCLK
I
This pin functions as the serial data clock for I/O operations.
41
SDIO
I/O
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
43
DVDD_I/O
I
Digital Power Supply (for I/O Cells Only, 3.3 V).
44
SYNC_IN
I
Input Signal Used to Synchronize Multiple AD9859s. This input is connected to the SYNC_CLK
output of a master AD9859.
45
SYNC_CLK
O
Clock Output Pin Serves as a Synchronizer for External Hardware.
46
OSK
I
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when
Programmed for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not
programmed, this pin should be tied to DGND.
<49>
AGND
I
The exposed paddle on the bottom of the package is a ground connection for the DAC and
must be attached to AGND in any board layout.


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