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ADSP-TS101S Datasheet(PDF) 11 Page - Analog Devices

No. de pieza ADSP-TS101S
Descripción Electrónicos  TigerSHARC Embedded Processor
Download  48 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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ADSP-TS101S Datasheet(HTML) 11 Page - Analog Devices

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ADSP-TS101S
Rev. C
|
Page 11 of 48
|
May 2009
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ integrated development and debugging envi-
ronment (IDDE) lets programmers define and manage DSP
software development. Its dialog boxes and property pages let
programmers configure and manage all of the TigerSHARC
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command-line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command-line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, examine run-time stack and heap usage. The Expert
Linker is fully compatible with existing linker definition file
(LDF), allowing the developer to move between the graphical
and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS101S processor to monitor and con-
trol the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modifi-
cation of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third-party software tools include DSP libraries, real-
time operating systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE
DSP BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-
erence on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-TS101S processor’s architecture and functionality.
For detailed information on the ADSP-TS101S processor’s core
architecture and instruction set, see the ADSP-TS101
TigerSHARC Processor Programming Reference and the
ADSP-TS101 TigerSHARC Processor Hardware Reference.
For detailed information on the development tools for this pro-
cessor, see the VisualDSP++ User’s Guide.


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