Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD7849BN Datasheet(PDF) 9 Page - Analog Devices |
|
AD7849BN Datasheet(HTML) 9 Page - Analog Devices |
9 / 15 page AD7849 REV. B –9– t2 t1 t3 t4 t5 t4 t5 t7 DB0 DB15 DB13 DB0 SCLK SYNC BIN/COMP SDIN (AD7849B/C/T) SDIN (AD7849A) LDAC, CLR DCEN IS TIED PERMANENTLY LOW Figure 12. Timing Diagram (Stand-Alone Mode) DIGITAL INTERFACE The AD7849 contains an input serial to parallel shift register and a DAC latch. A simplified diagram of the input loading circuitry is shown in Figure 12. Serial data on the SDIN input is loaded to the input register under control of DCEN, SYNC and SCLK. When a complete word is held in the shift register it may then be loaded into the DAC latch under control of LDAC. Only the data in the DAC latch determines the analog output on the AD7849. The DCEN (daisy-chain enable) input is used to select either a stand-alone mode or a daisy-chain mode. The loading format is slightly different depending on which mode is selected. Serial Data Loading Format (Stand-Alone Mode) With DCEN at Logic 0 the stand-alone mode is selected. In this mode a low SYNC input provides the frame synchronization signal which tells the AD7849 that valid serial data on the SDIN input will be available for the next 16 falling edges of SCLK. An internal counter/decoder circuit provides a low gating signal so that only 16 data bits are clocked into the input shift register. After 16 SCLK pulses the internal gating signal goes inactive (high) thus locking out any further clock pulses. Therefore ei- ther a continuous clock or a burst clock source may be used to clock in the data. The SYNC input is taken high after the complete 16-bit word is loaded in. The AD7849B, AD7849C and AD7849T versions are 16-bit resolution DACS and have a straight 16-bit load format, with the MSB (DB15) being loaded first. The AD7849A is a 14-bit DAC but the loading structure is still 16-bit. The MSB (DB13) is loaded first and the final two bits of the 16-bit stream must be 0s. There are two ways in which the DAC latch and hence the ana- log output may be updated. The status of the LDAC input is examined after SYNC is taken low. Depending on its status, one of two update modes is selected. If LDAC = 0 then the automatic update mode is selected. In this mode the DAC latch and analog output are updated auto- matically when the last bit in the serial data stream is clocked in. The update thus takes place on the sixteenth falling SCLK edge. If LDAC = 1 then the automatic update is disabled. The DAC latch update and output update are now separate. The DAC latch is updated on the falling edge of LDAC. However, the output update is delayed for a further 5 µs by means of an inter- nal track-and-hold amplifier in the output stage. This function results in lower digital-to-analog glitch impulse at the DAC output. Note that the LDAC input must be taken back high again before the next data transfer is initiated. ÷16 COUNTER/ DECODER RESET EN GATED SIGNAL INPUT SHIFT REGISTER (16 BITS) GATED SCLK SDOUT DCEN SYNC SCLK AUTO-UPDATE CIRCUITRY SDIN DAC LATCH (14/16 BITS) LDAC CLR Figure 13. Simplified Loading Structure |
Número de pieza similar - AD7849BN |
|
Descripción similar - AD7849BN |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |