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FM93C46A Datasheet(PDF) 4 Page - Fairchild Semiconductor

No. de Pieza. FM93C46A
Descripción  1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Descarga  13 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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FM93C46A Datasheet(HTML) 4 Page - Fairchild Semiconductor

 
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FM93C46A Rev. C.1
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature
-65
°C to +150°C
All Input or Output Voltages
+6.5V to -0.3V
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
+300
°C
ESD rating
2000V
Operating Conditions
Ambient Operating Temperature
FM93C46AL/LZ
0
°C to +70°C
FM93C46ALE/LZE
-40
°C to +85°C
FM93C46ALV/LZV
-40
°C to +125°C
Power Supply (V
CC)
2.7V to 5.5V
DC and AC Electrical Characteristics V
CC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for V
CC = 4.5V to 5.5V
Symbol
Parameter
Conditions
Min
Max
Units
I
CCA
Operating Current
CS = V
IH, SK=250 KHz
1
mA
ICCS
Standby Current
CS = VIL
L
10
µA
LZ (2.7V to 4.5V)
1
µA
I
IL
Input Leakage
V
IN = 0V to VCC
±1
µA
I
OL
Output Leakage
(Note 2)
I
ILO
Input Leakage ORG Pin
ORG tied to V
CC
-1
1
µA
ORG tied to V
SS (Note 3)
-2.5
2.5
VIL
Input Low Voltage
-0.1
0.15VCC
V
V
IH
Input High Voltage
0.8V
CC
V
CC +1
VOL
Output Low Voltage
IOL = 10µA
0.1VCC
V
V
OH
Output High Voltage
I
OH = -10µA
0.9V
CC
fSK
SK Clock Frequency
(Note 4)
0
250
KHz
t
SKH
SK High Time
1
µs
tSKL
SK Low Time
1
µs
t
CS
Minimum CS Low Time
(Note 5)
1
µs
t
CSS
CS Setup Time
0.2
µs
tDH
DO Hold Time
70
ns
t
DIS
DI Setup Time
0.4
µs
tCSH
CS Hold Time
0
ns
t
DIH
DI Hold Time
0.4
µs
t
PD
Output Delay
2
µs
tSV
CS to Status Valid
1
µs
t
DF
CS to DO in Hi-Z
CS = V
IL
0.4
µs
t
WP
Write Cycle Time
15
ms
Capacitance T
A = 25°C, f = 1 MHz or
250 KHz (Note 6)
Symbol
Test
Typ
Max
Units
C
OUT
Output Capacitance
5
pF
C
IN
Input Capacitance
5
pF
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3:
ORG pin may draw >1
µA when in x8 mode due to the internal pull-up transistor.
Note 4:
The shortest allowable SK clock period = 1/f
SK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/f
SK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5:
CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 6:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
VIL/VIH
VOL/VOH
IOL/IOH
Input Levels
Timing Level
Timing Level
2.7V
≤ V
CC ≤ 5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
±10µA
(Extended Voltage Levels)
4.5V
≤ V
CC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (C
L = 100 pF)


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