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FM93C46A Datasheet(PDF) 6 Page - Fairchild Semiconductor

No. de Pieza. FM93C46A
Descripción  1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Descarga  13 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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FM93C46A Datasheet(HTML) 6 Page - Fairchild Semiconductor

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FM93C46A Rev. C.1
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit (or 7-bit) address
information should be issued. For certain instructions, some of the
bits of this field are don’t care values (can be “0” or “1”), but they
should still be issued. Following the address information, depend-
ing on the instruction (WRITE and WRALL), 16-Bit data (or 8-Bit)
is issued. Otherwise, depending on the instruction (READ), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
7 instructions is explained in detail in the following sections.
1) Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under Table
1 or Table 2. Upon receiving a valid input information, decoding of
the opcode and the address is made, followed by data transfer
from the selected memory location into a 16-bit serial-out shift
register. This 16-bit data (or 8-bit data) is then shifted out on the
DO pin. MSB of the data (D15 or D8) is shifted out first and LSB
(DO) is shifted out last. A dummy-bit (logical 0) precedes this data
output string. Output data changes are initiated on the rising edge
of the SK clock. After reading the 16-bit (or 8-bit) data, the CS
signal can be brought low to end the Read cycle. Refer
Read cycle
diagram.
2) Write Enable (WEN)
When V
CC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations must be
preceded by a Write Enable (WEN) instruction. Once a Write
Enable instruction is executed, programming remains enabled
until a Write Disable (WDS) instruction is executed or V
CC is
completely removed from the part. Input information (Start bit,
Opcode and Address) for this WEN instruction should be issued
as listed under Table 1 or Table 2. The device becomes write-
enabled at the end of this cycle when the CS signal is brought low.
Execution of a READ instruction is independent of WEN instruc-
tion. Refer
Write Enable cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only when
device is write-enabled (Refer WEN instruction).
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table 1 or
Table 2. After inputting the last bit of data (D0 bit), CS signal must
be brought low before the next rising edge of the SK clock. This
falling edge of the CS initiates the self-timed programming cycle.
It takes t
WP time (refer appropriate DC and AC Electrical Charac-
teristics table) for the internal programming cycle to finish. During
this time, the device remains busy and is not ready for another
instruction.
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after t
CS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer
Write cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when device is write-enabled (Refer
WEN instruction).
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table 1 or
Table 2. After inputting the last bit of data (D0 bit), CS signal must
be brought low before the next rising edge of the SK clock. This
falling edge of the CS initiates the self-timed programming cycle.
It takes tWP time (Refer appropriate DC and AC Electrical Charac-
teristics table) for the internal programming cycle to finish. During
this time, the device remains busy and is not ready for another
instruction. Status of the internal programming can be polled as
described under WRITE instruction description. While the device
is busy, it is recommended that no new instruction be issued.
Refer
Write All cycle diagram.
Table 2. Instruction set (8-bit organization)
Instruction
Start Bit
Opcode Field
Address Field
Data Field
READ
1
10
A6
A5
A4
A3
A2
A1
A0
WEN
1
00
1
1
XXXXX
WRITE
1
01
A6
A5
A4
A3
A2
A1
A0
D7-D0
WRALL
1
00
0
1
XXXXX
D7-D0
WDS
1
00
0
0
XXXXX
ERASE
1
11
A6
A5
A4
A3
A2
A1
A0
ERAL
1
00
1
0
XXXXX


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