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AD9847AKCPZRL Datasheet(PDF) 4 Page - Analog Devices |
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AD9847AKCPZRL Datasheet(HTML) 4 Page - Analog Devices |
4 / 28 page REV. A AD9847 –4– TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit MASTER CLOCK (CLI) CLI Clock Period tCLI 25 ns CLI High/Low Pulsewidth tADC 12.5 ns Delay from CLI to Internal Pixel Period Position tCLIDLY 6ns EXTERNAL MODE CLAMPING CLPDM Pulsewidth tCDM 410Pixels CLPOB Pulsewidth * tCOB 220 Pixels SAMPLE CLOCKS SHP Rising Edge to SHD Rising Edge tS1 10 ns DATA OUTPUTS Output Delay from Programmed Edge tOD 6ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns SCK Falling Edge to SDATA Valid Read tDV 10 ns *Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference. Specifications subject to change without notice. (CL to 29 pF, fCLI = 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.) |
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