ADS62P29 datasheet(3/65 Pages) TI

No. de pieza	ADS62P29

Descripción Electrónicos	Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

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Fabricante Electrónico	TI [Texas Instruments]

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ADS62P19

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SLAS937 – APRIL 2013

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage

3.15

3.3

3.6

V

DRVDD

Digital supply voltage

1.7

1.8

1.9

V

ANALOG INPUTS

Differential input voltage range

2

VPP

Input common-mode voltage

1.5 ± 0.1

V

Voltage applied on CM in external reference mode

1.5 ± 0.05

V

With 2-Vpp input amplitude

(1)

500

MHz

Maximum analog input

frequency

With 1-Vpp input amplitude

(1)

800

MHz

CLOCK INPUT

Low-speed mode disabled (default mode after reset)

> 80

250(2)

MSPS

Input clock sample rate

Low-speed mode enabled(3)

1

80

MSPS

With multiplexed mode enabled(4)

1

65

MSPS

Sine wave, ac-coupled

0.2

1.5

VPP

Input clock amplitude

LVPECL, ac-coupled

1.6

VPP

differential

LVDS, ac-coupled

0.7

VPP

(VCLKP – VCLKM)

(5) (6)

LVCMOS, single-ended, ac-coupled

3.3

V

Input clock duty cycle

40%

50%

60%

DIGITAL OUTPUTS

CLOAD

Maximum external load capacitance from each output pin to DRGND

5

pF

RLOAD

Differential load resistance between the LVDS output pairs (LVDS mode)

100

Ω

TA

Operating free-air temperature

–40

85

°C

(1)

See the Theory of Operation section for information.

(2)

With LVDS interface only; maximum recommended sample rate with CMOS interface is 210 MSPS.

(3)

Use the ENABLE LOW SPEED MODE register bit; refer to the Serial Register Map section for information.

(4)

See the Multiplexed Output Mode section for information.

(5)

Refer to Figure 25.

(6)

Refer to Figure 1 for the definition of clock amplitude.

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