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ADS5403 Datasheet(PDF) 5 Page - Texas Instruments

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No. de pieza ADS5403
Descripción Electrónicos  Dual Channel 12-Bit 500Msps Analog-to-Digital Converter
Download  40 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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ADS5403 Datasheet(HTML) 5 Page - Texas Instruments

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ADS5404
www.ti.com
SLAS945 – APRIL 2013
PACKAGE/ORDERING INFORMATION
SPECIFIED
TRANSPORT
ECO
ORDERING
PACKAGE-
PACKAGE
LEAD/BALL
PACKAGE
PRODUCT
TEMPERATURE
MEDIA,
LEAD
DESIGNATOR
FINISH
MARKING
NUMBER
PLAN(2)
RANGE
QUANTITY
GREEN
ADS5404IZAY
Tray
ADS5404
196-BGA
ZAY
–40°C to 85°C
ADS5404I
(RoHS & no
ADS5404IZAYR
Tape and Reel
Sb/Br)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
MAX
Supply voltage range, AVDD33
–0.5
4
V
Supply voltage range, AVDDC
–0.5
2.3
V
Supply voltage range, AVDD18
–0.5
2.3
V
Supply voltage range, DVDD
–0.5
2.3
V
Supply voltage range, DVDDLVDS
–0.5
2.3
V
Supply voltage range, IOVDD
–0.5
4
V
INA/B_P, INA/B_N
–0.5
AVDD33 + 0.5
V
CLKINP, CLKINN
–0.5
AVDDC + 0.5
V
Voltage applied to input pins
SYNCP, SYNCN
–0.5
AVDD33 + 0.5
V
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
–0.5
IOVDD + 0.5
V
Operating free-air temperature range, TA
–40
85
°C
Operating junction temperature range, TJ
150
°C
Storage temperature range
–65
150
°C
ESD, Human Body Model
2
kV
THERMAL INFORMATION
ADS5404
THERMAL METRIC(1)
nFBGA
UNITS
196 PINS
θJA
Junction-to-ambient thermal resistance(2)
37.6
θJCtop
Junction-to-case (top) thermal resistance(3)
6.8
θJB
Junction-to-board thermal resistance(4)
16.8
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.2
ψJB
Junction-to-board characterization parameter(6)
16.4
spacer
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2013, Texas Instruments Incorporated
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