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6

Physical Dimensions

2.65 M AX

0.20±0.10

0.10 C

C

15.40±0.20

A

SEE D ETAIL A

0.33

0.20

NO TES: UNLESS O THERW ISE SPECIFIED

A) TH IS PAC KAG E C O NFO RM S TO JEDEC

M S-013, ISSU E E, DATED SEPT 2005.

B) ALL D IM EN SIO N S ARE IN M ILLIM ETERS.

C) DIM ENSIO NS DO NO T INCLUDE M O LD

FLASH O R BURRS.

D ) LAN D PATER N STAN D AR D : SO IC127P1030X265-24L

PIN O NE

INDICATO R

10.325

24

13

13.970

7.50±0.10

B

X 45°

0.75

0.25

(R 0.10)

(R0.10)

0.40~1.27

8°

0°

SEATIN G PLANE

(1.40)

0.25

GAGE PLAN E

DETAIL A

SC ALE: 2:1

SEATIN G PLANE

112

0.25

0.51

0.35

B

CA

M

1.27

LAND PATTER N RECO M M EN DATIO N

14.52

1.27 TYP

0.55 TYP

1.75 TYP

9.2

10.95

E) DRAW ING FILENAM E: M KT-M 24BREV2

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may

change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fair-

child Semiconductor representative to verify or obtain the most recent revision. Package specifications do not

expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: