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AD1853JRS Datasheet(PDF) 8 Page - Analog Devices |
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AD1853JRS Datasheet(HTML) 8 Page - Analog Devices |
8 / 16 page REV. A AD1853 –8– In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse, and that synchronism is maintained from that point forward. Note that the AD1853 is capable of a 32 × FS BCLK frequency “packed mode” where the MSB is left-justified to an L/ RCLK transition, and the LSB is right-justified to the opposite L/ RCLK transition. L/ RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1853 is programmed in right- justified or left-justified mode. Packed mode is shown is Figure 5. Master Clock Auto-Divide Feature The AD1853 has a circuit that autodetects the relationship between master clock and the incoming serial data, and inter- nally sets the correct divide ratio to run the interpolator and modulator. The allowable frequencies for each mode are shown above. Serial Control Port The AD1853 serial control port is SPI-compatible. SPI (Serial Peripheral Interface) is an industry standard serial port protocol. The write-only serial control port gives the user access to: select input mode, soft reset, soft de-emphasis, channel specific at- tenuation and mute (both channels at once). The SPI port is a 3-wire interface with serial data (CDATA), serial bit clock (CCLK), and data latch (CLATCH). The data is clocked into an internal shift register on the rising edge of CCLK. The serial data should change on the falling edge of CCLK and be stable on the rising edge of CCLK. The rising edge of CLATCH is used internally to latch the parallel data from the serial-to-parallel converter. This rising edge should be aligned with the falling edge of the last CCLK pulse in the 16-bit frame. The CCLK can run continuously between transactions. The serial control data is 16-bit MSB first, and is unsigned. Bits 0 and 1 are used to select 1 of 3 registers (control, volume left, and volume right). The remaining 14 bits (bits 15:2) are used to carry the data for the selected register. If a volume register is selected, then the upper 14 bits are used to multiply the digital input signal by the control word, which is interpreted as an unsigned number (for example, 11111111111111 is 0 dB, and 01111111111111 is –6 dB, etc.). The default volume control words on power-up are all 1s (0 dB). The control register only uses bits 11:2 to carry data; the upper bits (15:12) should al- ways be written with zeroes, as several test modes are decoded from these upper bits. The control register defaults on power-up to 8 × interpolation mode, 24-bit right-justified serial mode, unmuted, and no de-emphasis filter. The intent with these reset defaults is to enable AD1853 applications without requiring the use of the serial control port. For those users that do not use the serial control port, it is still possible to mute the AD1853 output by using the MUTE pin (Pin 23) signal. Note that the serial control port timing is asynchronous to the serial data port timing. Changes made to the attenuator level will be updated on the next edge of the LRCLK after CLATCH write pulse as shown in Figure 6. Table II. Nominal Input Internal Sigma-Delta Chip Mode Allowable Master Clock Frequencies Sample Rate Clock Rate INT8 × Mode 256 × FS, 384 × FS, 512 × FS, 768 × FS, 1024 × FS 48 kHz 128 × FS INT4 × Mode 128 × F S, 192 × F S, 256 × F S, 384 × F S, 512 × F S 96 kHz 64 × F S INT2 × Mode 64 × FS, 96 × FS, 128 × FS, 192 × FS, 256 × FS 192 kHz 32 × FS D15 D14 D0 tCHD tCCH tCSU tCCL tCLL tCLH CDATA CCLK CLATCH Figure 7. Serial Control Port Timing |
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