REV. A

AD7899

–6–

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Description

Reference Input/Output. This pin is provides access to the internal reference (2.5 V

± 20 mV) and

also allows the internal reference to be overdriven by an external reference source (2.5 V

± 5%).

A 0.1

µF decoupling capacitor should be connected between this pin and GND.

2, 6

GND

Ground Pin. This pin should be connected to the system’s analog ground plane.

3, 4

Analog Inputs. See Analog Input Section.

Positive Supply Voltage, 5.0 V

± 5%.

7–13

DB13–DB7

Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs.

14

OPGND

Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/

EOC. It should

be connected to the system’s analog ground plane .

15

but may also be powered by a 3 V

± 10% supply which allows the inputs and outputs to be interfaced

µF capacitor to GND.

16–22

DB6–DB0

Data Bit 6 to Data Bit 0. Three-state Outputs.

23

BUSY/

EOC

BUSY/

EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion

has finished. The function of the BUSY/

EOC is determined by the state of CONVST at the end of con-

version. See the Timing and Control Section.

24

RD

Read Input. Active low logic input which is used in conjunction with

CS low to enable the data outputs.

25

CS

Chip Select Input. Active low logic input. The device is selected when this input is active.

26

CONVST

Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode

and starts conversion.

27

CLKIN

Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the

conversion rate of the AD7899. If the CLKIN input is high on the rising edge of

CONVST an externally

applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of

CONVST

the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock

cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle

no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required.

28

STBY

Standby Mode Input. Logic input which is used to put the device into the power save or standby mode.

The

STBY input is high for normal operation and low for standby operation.

PIN CONFIGURATION

SOIC/SSOP

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD7899

OPGND

DB7

DB8

DB9

DB10

DB11

DB12

GND

DB13

GND

DB6

DB5

DB4

DB3

DB2

DB1

STBY

CLKIN

CONVST

CS

DB0

BUSY/

EOC

RD