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AN32055A Datasheet(PDF) 3 Page - Panasonic Semiconductor |
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AN32055A Datasheet(HTML) 3 Page - Panasonic Semiconductor |
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3 / 97 page  AN32055A Page 3 of 96 Product Standards ABSOLUTE MAXIMUM RATINGS — V – 0.3 to 6.5 BL1, BL2, BL3, BL4, BLS1, BLS2, PL1, PL2, R1, G1, B1, R2, G2, B2, LDO1, LDO2, LX, X0, X1, X2, X3, X4, X5, X6, Y0, Y1, Y2, Y3, Y4, Y5, Y6 — V – 0.3 to 6.0 LDO1, LDO2 — V – 0.3 to 6.0 LEDCNT, LDOCNT, FB *1 V 6.5 VLEDMAX — V – 0.3 to 3.4 GPO1, GPO2, INT, DO Output Voltage Range *2 C – 30 to + 125 Tj Operating junction temperature — V – 0.3 to 3.4 LEDCTL, RSTB, CSB, CLK, DI, EXTCLK, VIBCTL, GPI1, GPI2, GPI3, GPIO1, GPIO2 Input Voltage Range *2 C –55to+ 125 Tstg Storage temperature — kV 1.0to1.5 HBM ESD Note Unit Rating Symbol Parameter *2 C –30 to + 85 Topr Operating ambience temperature *1 V 6.0 VBMAX Supply voltage 0.335 W 0.837 W 119.4 C /W 80 pin Wafer level chip size package (WLCSP) PD (Ta=85 C) PD (Ta=25 C) JA PACKAGE POWER DISSIPATION RATING Note) For the actual usage, please refer to the P D-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. This value is based on the data LSI mount on PCB Grass Epoxy : 50 X 50 X 0.8 t ( mm ). CAUTION Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1: VB MAX = VBDCDC = VBLED = VB, VLEDMAX = VLED1 = VLED2. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 C. Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates. Doc No. TA4-EA-04511 Revision. 2 Established : 2006-08-29 Revised : 2013-04-01 |
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