ADG211AKR datasheet(5/16 Pages) AD

No. de pieza	ADG211AKR

Descripción Electrónicos	LC2MOS Quad SPST Switches

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Data Sheet

ADG211A/ADG212A

Rev. C | Page 5 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. PDIP, SOIC Pin Configuration

Figure 4. PLCC Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

PDIP, SOIC

PLCC

1

2

IN1

Logic Control Input.

2

3

D1

Drain Terminal. Can be an input or output.

3

4

S1

Source Terminal. Can be an input or output.

4

5

VSS

Most Negative Power Supply Potential.

5

7

GND

Ground (0 V) Reference.

6

8

S4

Source Terminal. Can be an input or output.

7

9

D4

Drain Terminal. Can be an input or output.

8

10

IN4

Logic Control Input.

9

12

IN3

Logic Control Input.

10

13

D3

Drain Terminal. Can be an input or output.

11

14

S3

Source Terminal. Can be an input or output.

12

15

VL

Logic Supply Voltage.

13

17

VDD

Most Positive Power Supply Potential.

14

18

S2

Source Terminal. Can be an input or output.

15

19

D2

Drain Terminal. Can be an input or output.

16

20

IN2

Logic Control Input.

1, 6, 11, 16

NIC

No Internal Connection.

Table 4. Truth Table

ADG211A In

ADG212A In

Switch Condition

0

1

On

1

0

Off

IN1

1

D1

2

S1

3

VSS 4

IN2

16

D2

15

S2

14

VDD

13

GND

5

S4

6

D4

7

VL

12

S3

11

D3

10

IN4

8

IN3

9

ADG211A/

ADG212A

TOP VIEW

(Not to Scale)

NOTES

1. NIC = NO INTERNAL CONNECTION.

1

20

19

2

3

4

5

6

7

8

18

17

16

15

14

9

10

11

12

13

S1

VSS

NIC

GND

S4

S2

VDD

NIC

VL

S3

PIN 1

INDENTFIER

ADG211A/

ADG212A

TOP VIEW

(Not to Scale)

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