IRF7404 datasheet(2/22 Pages) AD

No. de pieza	IRF7404

Descripción Electrónicos	Thermoelectric Cooler Controller

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Fabricante Electrónico	AD [Analog Devices]

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REV.

–2–

ADN8830–SPECIFICATIONS

(@ VDD = 3.3 V to 5.0 V, VGND = 0 V, TA = 25 C, TSET = 25 C, using typical application

configuration as shown in Figure 1, unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

TEMPERATURE STABILITY

Long-Term Stability

Using 10 k

Ω thermistor with

= –4.4% at 25

°C

0.01

°C

PWM OUTPUT DRIVERS

Output Transition Time

tR, tF

CL = 3,300 pF

20

ns

Nonoverlapping Clock Delay

50

65

ns

Output Resistance

RO (N1, P1)

IL = 50 mA

6

Ω

Output Voltage Swing

OUT A

VLIM = 0 V

0

VDD

V

Output Voltage Ripple

OUT A

fCLK = 1 MHz

0.2

%

Output Current Ripple

ITEC

fCLK = 1 MHz

0.2

%

LINEAR OUTPUT AMPLIFIER

Output Resistance

RO, P2

IOUT = 2 mA

85

Ω

RO, N2

IOUT = 2 mA

178

Ω

Output Voltage Swing

OUT B

0

VDD

V

POWER SUPPLY

Power Supply Voltage

VDD

3.0

5.5

V

Power Supply Rejection Ratio

PSRR

VDD = 3.3 V to 5 V, VTEC = 0 V

80

92

dB

–40

°C ≤ T

A

≤ +85°C60

dB

Supply Current

ISY

PWM not switching

8

12

mA

–40

°C ≤ TA ≤ +85°C15

mA

Shutdown Current

ISD

Pin 10 = 0 V

5

μA

Soft-Start Charging Current

ISS

15

μA

Undervoltage Lockout

VOLOCK

Low-to-high threshold

2.0

2.7

V

ERROR AMPLIFIER

Input Offset Voltage

VOS

VCM = 1.5 V

50

250

μV

Gain

AV, IN

20

V/V

Input Voltage Range

VCM

0.2

2.0

V

Common-Mode Rejection Ratio

CMRR

0.2 V < VCM < 2.0 V

58

68

dB

–40

°C ≤ TA ≤ +85°C55

dB

Open-Loop Input Impedance

RIN

1G

Ω

Gain-Bandwidth Product

GBW

2

MHz

REFERENCE VOLTAGE

Reference Voltage

VREF

IREF < 2 mA

2.37

2.47

2.57

V

OSCILLATOR

Synchronization Range

fCLK

Pin 25 connected to external clock

200

1,000

kHz

Oscillator Frequency

fCLK

Pin 24 = VDD; (R = 150 k

Ω;

800

1,000

1,250

kHz

Pin 25 = GND)

LOGIC CONTROL

*

Logic Low Input Threshold

0.2

V

Logic High Input Threshold

3

V

Logic Low Output Level

0.2

V

Logic High Output Threshold

VDD – 0.2

V

*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1

μA).

Specifications subject to change without notice.

D

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