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DAC1220E Datasheet(PDF) 7 Page - Texas Instruments |
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DAC1220E Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 26 page  DAC1220 www.ti.com...................................................................................................................................... SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009 Output Digital Connections The output voltage range is nominally 0V to 2 × VREF. The digital lines, except for the crystal oscillator lines, It does not go below ground. The output amplifier is operate at TTL-compatible CMOS logic levels. They not designed for heavy loads; it can drive a maximum can be driven from 3.3V logic sources. of 0.5mA. At power-on and during sleep mode, the In noise-sensitive applications, it may be helpful to amplifier is disconnected, so the output is high keep the level transition rates on the digital lines impedance. slow. Fast transitions can couple through the device The output is not fully linear to the rails; maximum to the output, causing noise. Rate limiting can be linearity is specified from (AGND + 20mV) to (AVDD – done with resistance or even an RC filter. 20mV). For linearity from 0–5V, AVDD can be increased to 5.02V or more, and AGND can be Clock Oscillator decreased to –20mV or less. As long as the specified The DAC1220 has a built-in crystal oscillator at pins operating limits are observed, this will not damage XIN and XOUT. To use it, connect a crystal and load the device. capacitors as shown in Figure 5. Filter Capacitors 12pF load capacitors are shown in the schematic, but the correct value depends mainly on the crystal and The continuous-time output filter requires two external layout, and not on the oscillator itself. Load capacitors to operate. The recommended values of capacitance affects startup time, oscillation these capacitors depend on whether the DAC1220 frequency, and reliability. If startup is unreliable, try will be operated in 16-bit or 20-bit mode, and are lowering the capacitor values. Remember that shown in Table 1. parasitic board and pin capacitance can be a significant portion of the crystal load capacitance. Table 1. Filter Capacitor Values When the crystal oscillator is operating, a sinusoidal CAPACITOR 16-BIT MODE 20-BIT MODE signal of relatively low amplitude will be observed at C1 2.2nF 10nF both the XIN and XOUT pins. C2 0.22nF 3.3nF The typical frequency to use with the DAC1220 is The capacitors should be stable and high grade. Film 2.5MHz. Deviating too far from this may alter noise types, or other capacitors designed for precision and settling time, as well as timing characteristics. filtering, are strongly recommended. Low-quality capacitors will degrade performance significantly. Connecting an External Clock The C1 and C2 pins are very sensitive. It is critical to An external clock signal can be connected at XIN. A surround them with a guard ring at the reference CMOS or TTL logic signal can be used. If an external voltage for best noise performance. See the Layout clock signal is used, XOUT should be left unconnected. section for more information. In some cases, an RC filter on the clock line may reduce noise. Voltage Reference The voltage reference input is designed for +2.5V. At this voltage, the output will range from ground to approximately 5V, as noted above. Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DAC1220 |
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