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TPS65642YFFR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65642YFFR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 70 page  TPS65642 SLVSBX6 – JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.3 V, VCORE = 1.1 V, VIO1 = 1.7 V, VIO2 = 1.8 V (1), AV DD = 8.1 V, VGH = 24 V, TA = −40°C to 85°C. Typical values are at 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Offset Code = 512 –25 25 mV INL Integral nonlinearity No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V –3.6 5.9 LSB DNL Differential nonlinearity No load, VGAMH = AVDD – 0.25 V, VGAML = 0.25 V –1 1.5 LSB PROGRAMMABLE VCOM CALIBRATOR SETZSE Set zero-scale error –1 1 LSB SETFSE Set full-scale error –7 7 LSB VRSET Voltage on RSET pin IRSET=50 µA –2% 1.25 2% V DNL Differential nonlinearity –1 1.5 LSB VCM = AVDD/2, VOUT1 = 2 V, VOUT2 = AVDD – 2 V, RL= AVOL Open loop gain 70 91 dB ∞ VIO Input offset voltage VCM = AVDD/2, VOUT = AVDD/2 –15 15 mV IB Input bias current VCM = AVDD/2, VOUT = AVDD/2 –150 150 nA VPOS = AVDD/2, VNEG = AVDD/2–1 V, VDROPH High-side voltage drop 0.05 0.1 V IOUT = 10 mA sourcing VPOS = AVDD/2, VNEG = AVDD/2+1 V, VDROPL Low-side voltage drop 0.03 0.1 V IOUT = 10 mA sinking High-side peak output current 200 294 VCM = AVDD/2, VSIGNAL = 2 VPP, open-loop, IPK mA RL = ∞, CL = 1 µF Low-side peak output current –349 –200 CMRR Common-mode rejection ratio VCM1 = 2 V, VCM2 = AVDD–2 V, VOUT = AVDD/2 40 78 dB PSRR Power supply rejection ratio AVDD1 = 6 V, AVDD2 = 9.1 V, VCM = 3 V, VOUT = 3 V 40 110 dB TA = –40°C 18 30 Open-loop, SR Slew rate V/ μs VPOS = AVDD/2±1 V TA = 25°C to 85°C 25 38 GATE VOLTAGE SHAPING VGH to VGHM ON resistance VGH = 24 V, IGHM = 10 mA, FLK = 2.5 V 12 25 rDS(ON) VGHM = 24 V, IGHM = 10 mA, FLK = 0 V 12 25 Ω VGHM to RE ON resistance VGHM = 6 V, IGHM = 10 mA, FLK = 0 V 12 25 VGHM rising, 2.5 V, 50% thresholds, COUT = 150 pF, RE tPLH 72 175 = 0 Ω Propagation delay ns VGHM falling, 2.5 V, 50% thresholds, COUT = 150 pF, tPHL 81 200 RE = 0 Ω PANEL RESET / LCD BIAS READY (XAO) VOL Low output voltage I XAO = 1 mA (sinking) 0.23 0.5 V IOH High output current V XAO = 2.5 V 1 µA XAO threshold voltage 2.2 3.9 XAO falling VDET Tolerance –2.5% 2.5% V Hysteresis XAO rising 3% 6.3% 11% TIMING Boost converter 1 delay range 0 70 tDLY1 ms Tolerance –20% 30% Gate voltage shaping / LCD bias 0 35 ready delay range tDLY6 ms Tolerance –20% 30% Soft-start ramp time 0.5 4 tSS1 VCORE, VIO1, VIO2 ms Tolerance –20% 30% Soft-start ramp time 4.0 7.5 tSS2 AVDD, VGH ms Tolerance –20% 30% tUVP Undervoltage protection timeout 40 50 65 ms I2C INTERFACE Configuration parameters slave 74h address ADDR Programmable VCOM slave address 4Fh VIL Low level input voltage Rising Edge, standard and fast mode 0.75 V 6 Electrical Specifications Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65642 |
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