 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD9779ABSVZRL Datasheet(PDF) 6 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD9779ABSVZRL Datasheet(HTML) 6 Page - Analog Devices |
|
|
6 / 56 page  AD9776A/AD9778A/AD9779A Rev. B | Page 6 of 56 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 2.0 V Input VIN Logic Low 0.8 V Maximum Input Data Rate at Interpolation 1× 300 MSPS 2× 250 MSPS 4× 200 MSPS 8× DVDD18, CVDD18 = 1.8 V ± 5% 112.5 MSPS DVDD18, CVDD18 = 1.9 V ± 5% 125 MSPS DVDD18, CVDD18 = 2.0 V ± 2% 137.5 MSPS CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1 Output VOUT Logic High 2.4 V Output VOUT Logic Low 0.4 V DATACLK Output Duty Cycle At 250 MHz, into 5 pF load 40 50 60 % LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate Additional limits on fSYNC_I apply; see description of Register 0x05, Bits[3:1], in Table 14 250 MSPS Setup Time, SYNC_I to REFCLK 0.4 ns Hold Time, SYNC_I to REFCLK 0.55 ns LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, RO Single-ended 80 100 120 Ω DAC CLOCK INPUT (REFCLK+, REFCLK−) Differential Peak-to-Peak Voltage 400 800 2000 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate DVDD18, CVDD18 = 1.8 V ± 5%, PLL off 900 MHz DVDD18, CVDD18 = 1.9 V ± 5%, PLL off 1000 MHz DVDD18, CVDD18 = 2.0 V ± 2%, PLL off 1100 MHz DVDD18, CVDD18 = 2.0 V ± 2%, PLL on 250 MHz 1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal. |
Número de pieza similar - AD9779ABSVZRL |
|
Descripción similar - AD9779ABSVZRL |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
